Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications

Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications. Li, J., Kang, K., & Roy, K. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(1):46–59, Jan, 2009.
doi bibtex

@ARTICLE{li2009tcad, 
author={Jing Li and Kunhyuk Kang and Kaushik Roy}, 
journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, 
title={Variation Estimation and Compensation Technique in Scaled {LTPS} {TFT} Circuits for Low-Power Low-Cost Applications}, 
year={2009}, 
volume={28}, 
number={1}, 
pages={46--59}, 
keywords={journal, CMOS integrated circuits,circuit reliability,elemental semiconductors,low-power electronics,silicon,statistical analysis,thin film transistors,CMOS technology,Si,circuit reliability,compensation technique,delay variation,four-finger structure,inverter chain,low-power low-cost application,low-temperature polycrystalline-silicon thin-film transistor,multifinger design technique,multimodal delay distribution,response surface method,statistical simulation methodology,unimodal distribution,variation estimation,CMOS logic circuits,CMOS technology,Circuit simulation,Delay,Grain boundaries,Logic devices,Response surface methodology,Robustness,Substrates,Thin film transistors,Grain boundary (GB),low-temperature polycrystalline-silicon (LTPS),process variation,thin-film transistor (TFT)}, 
doi={10.1109/TCAD.2008.2009149}, 
ISSN={0278-0070}, 
month={Jan},
keywords={journal}}

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