A compact low-power VLSI architecture for real-time sleep stage classification

A compact low-power VLSI architecture for real-time sleep stage classification. Li, P. Z. X., Kassiri, H., & Genov, R. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pages 1314–1317, 2016. IEEE.

Paper doi bibtex

@inproceedings{DBLP:conf/iscas/LiKG16,
  author       = {Peter Zhi Xuan Li and
                  Hossein Kassiri and
                  Roman Genov},
  title        = {A compact low-power {VLSI} architecture for real-time sleep stage
                  classification},
  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
                  Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
  pages        = {1314--1317},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISCAS.2016.7527490},
  doi          = {10.1109/ISCAS.2016.7527490},
  timestamp    = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iscas/LiKG16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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