1 Mb 0.41 $μ$m$^2$ 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (invited)

1 Mb 0.41 $μ$m$^2$ 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (invited). Li, J., Montoye, R., Ishii, M., & Chang, L. IEEE Journal of Solid-State Circuits, 49(4):896–907, April, 2014.
doi abstract bibtex

This work demonstrates the first fabricated 1 Mb nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90 nm CMOS technology and mushroom phase-change memory (PCM) technology. The primary challenge for enabling reliable array operation with such aggressive cell is presented, namely, severely degraded sensing margin due to significantly lower ON/OFF ratio of resistive memories ( 10 2 for PCM) than that of traditional MOSFETs (>10 5 ). To address this challenge, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding and 2) a clocked self-referenced sensing scheme (CSRSS). In addition, the two-bit encoding can also improve algorithmic mapping by effectively compressing TCAM entries. The 1 Mb chip demonstrates reliable low voltage search operation (VDDmin 750 mV) and a match delay of 1.9 ns under nominal operating conditions.

@ARTICLE{li2014jssc, 
author={Jing Li and Robert Montoye and Masatoshi Ishii and Leland Chang}, 
journal={IEEE Journal of Solid-State Circuits}, 
title={1 {Mb} 0.41 {$\mu$m$^2$} {2T-2R} cell nonvolatile {TCAM} with two-bit encoding and clocked self-referenced sensing (<strong>invited</strong>)}, 
year={2014}, 
volume={49}, 
number={4}, 
pages={896--907}, 
keywords={journal, content-addressable storage,encoding,phase change memories,2T 2R cell nonvolatile TCAM,CMOS technology,algorithmic mapping,clocked self referenced sensing,phase change memory technology,resistive memories,size 90 nm,time 1.9 ns,two bit encoding,Arrays,Encoding,Microprocessors,Phase change materials,Random access memory,Sensors,Associative computing,encoding,hardware accelerator,intrusion detection,matchline compensation,nonvolatile,packet classification,phase change memory (PCM),search engine,self-referenced sensing,ternary content addressable memory (TCAM)}, 
abstract={This work demonstrates the first fabricated 1 Mb nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90 nm CMOS technology and mushroom phase-change memory (PCM) technology. The primary challenge for enabling reliable array operation with such aggressive cell is presented, namely, severely degraded sensing margin due to significantly lower ON/OFF ratio of resistive memories (~10 2 for PCM) than that of traditional MOSFETs (>10 5 ). To address this challenge, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding and 2) a clocked self-referenced sensing scheme (CSRSS). In addition, the two-bit encoding can also improve algorithmic mapping by effectively compressing TCAM entries. The 1 Mb chip demonstrates reliable low voltage search operation (VDDmin ~750 mV) and a match delay of 1.9 ns under nominal operating conditions.},
doi={10.1109/JSSC.2013.2292055}, 
ISSN={0018-9200}, 
month={April},
}

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