1Mb 0.41 $μ$m$^2$ 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (Highlight Paper of the Year)

1Mb 0.41 $μ$m$^2$ 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (Highlight Paper of the Year). Li, J., Montoye, R., Ishii, M., Stawiasz, K., Nishida, T., Maloney, K., Ditlow, G., Lewis, S., Maffitt, T., Jordan, R., & others In 2013 Symposium on VLSI Circuits, pages C104–C105, June, 2013. (Acceptance Rate: 27%, 109 out of 396)
abstract bibtex

This work demonstrates the first fabricated nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90nm CMOS technology and mushroom phase-change memory (PCM) process. To ensure reliable search operation with such compact cells, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding, and 2) a clocked self-referenced sensing scheme (CSRSS). The 1Mb chip demonstrates reliable low voltage search operation (VDDmin 750mV) and a match delay of 1.9 ns under nominal operating conditions.

@INPROCEEDINGS{li2013vlsi, 
author={Li, Jing and Montoye, Robert and Ishii, Masatoshi and Stawiasz, Kevin and Nishida, Takeshi and Maloney, Kim and Ditlow, Gary and Lewis, Scott and Maffitt, Tom and Jordan, Richard and others},
booktitle={2013 Symposium on VLSI Circuits}, 
title={{1Mb} 0.41 {$\mu$m$^2$} {2T-2R} cell nonvolatile {TCAM} with two-bit encoding and clocked self-referenced sensing (<strong>Highlight Paper of the Year</strong>)}, 
year={2013}, 
date={2013-06-12},
volume={}, 
number={}, 
pages={C104--C105}, 
keywords={conference, CMOS memory circuits,SRAM chips,clocks,content-addressable storage,integrated circuit design,integrated circuit reliability,low-power electronics,phase change memories,search problems,2-transistor-2-resistive-storage cells,2T-2R cells,CSRSS,IBM CMOS technology,PCM process,SRAM-based TCAM,bit rate 1 Mbit/s,cell nonvolatile TCAM,cell size,clocked self-referenced sensing scheme,compact cells,fabricated nonvolatile TCAM,low voltage search operation,match delay,mushroom phase-change memory process,reliable search operation,size 90 nm,technology node,test chip design,two-bit encoding,Arrays,Clocks,Encoding,Microprocessors,Phase change materials,Sensors}, 
doi={}, 
ISSN={2158-5601}, 
month={June},
abstract={This work demonstrates the first fabricated nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90nm CMOS technology and mushroom phase-change memory (PCM) process. To ensure reliable search operation with such compact cells, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding, and 2) a clocked self-referenced sensing scheme (CSRSS). The 1Mb chip demonstrates reliable low voltage search operation (VDDmin~750mV) and a match delay of 1.9 ns under nominal operating conditions.},
note = {(Acceptance Rate: <u>27\%</u>, 109 out of 396)}
}

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{"_id":"Rfr6WJdX25Te9zyGF","bibbaseid":"li-montoye-ishii-stawiasz-nishida-maloney-ditlow-lewis-etal-1mb041m22t2rcellnonvolatiletcamwithtwobitencodingandclockedselfreferencedsensingstronghighlightpaperoftheyearstrong-2013","author_short":["Li, J.","Montoye, R.","Ishii, M.","Stawiasz, K.","Nishida, T.","Maloney, K.","Ditlow, G.","Lewis, S.","Maffitt, T.","Jordan, R.","others"],"bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"propositions":[],"lastnames":["Li"],"firstnames":["Jing"],"suffixes":[]},{"propositions":[],"lastnames":["Montoye"],"firstnames":["Robert"],"suffixes":[]},{"propositions":[],"lastnames":["Ishii"],"firstnames":["Masatoshi"],"suffixes":[]},{"propositions":[],"lastnames":["Stawiasz"],"firstnames":["Kevin"],"suffixes":[]},{"propositions":[],"lastnames":["Nishida"],"firstnames":["Takeshi"],"suffixes":[]},{"propositions":[],"lastnames":["Maloney"],"firstnames":["Kim"],"suffixes":[]},{"propositions":[],"lastnames":["Ditlow"],"firstnames":["Gary"],"suffixes":[]},{"propositions":[],"lastnames":["Lewis"],"firstnames":["Scott"],"suffixes":[]},{"propositions":[],"lastnames":["Maffitt"],"firstnames":["Tom"],"suffixes":[]},{"propositions":[],"lastnames":["Jordan"],"firstnames":["Richard"],"suffixes":[]},{"firstnames":[],"propositions":[],"lastnames":["others"],"suffixes":[]}],"booktitle":"2013 Symposium on VLSI Circuits","title":"1Mb 0.41 $μ$m$^2$ 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (Highlight Paper of the Year)","year":"2013","date":"2013-06-12","volume":"","number":"","pages":"C104–C105","keywords":"conference, CMOS memory circuits,SRAM chips,clocks,content-addressable storage,integrated circuit design,integrated circuit reliability,low-power electronics,phase change memories,search problems,2-transistor-2-resistive-storage cells,2T-2R cells,CSRSS,IBM CMOS technology,PCM process,SRAM-based TCAM,bit rate 1 Mbit/s,cell nonvolatile TCAM,cell size,clocked self-referenced sensing scheme,compact cells,fabricated nonvolatile TCAM,low voltage search operation,match delay,mushroom phase-change memory process,reliable search operation,size 90 nm,technology node,test chip design,two-bit encoding,Arrays,Clocks,Encoding,Microprocessors,Phase change materials,Sensors","doi":"","issn":"2158-5601","month":"June","abstract":"This work demonstrates the first fabricated nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90nm CMOS technology and mushroom phase-change memory (PCM) process. To ensure reliable search operation with such compact cells, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding, and 2) a clocked self-referenced sensing scheme (CSRSS). The 1Mb chip demonstrates reliable low voltage search operation (VDDmin 750mV) and a match delay of 1.9 ns under nominal operating conditions.","note":"(Acceptance Rate: 27%, 109 out of 396)","bibtex":"@INPROCEEDINGS{li2013vlsi, \nauthor={Li, Jing and Montoye, Robert and Ishii, Masatoshi and Stawiasz, Kevin and Nishida, Takeshi and Maloney, Kim and Ditlow, Gary and Lewis, Scott and Maffitt, Tom and Jordan, Richard and others},\nbooktitle={2013 Symposium on VLSI Circuits}, \ntitle={{1Mb} 0.41 {$\\mu$m$^2$} {2T-2R} cell nonvolatile {TCAM} with two-bit encoding and clocked self-referenced sensing (Highlight Paper of the Year)}, \nyear={2013}, \ndate={2013-06-12},\nvolume={}, \nnumber={}, \npages={C104--C105}, \nkeywords={conference, CMOS memory circuits,SRAM chips,clocks,content-addressable storage,integrated circuit design,integrated circuit reliability,low-power electronics,phase change memories,search problems,2-transistor-2-resistive-storage cells,2T-2R cells,CSRSS,IBM CMOS technology,PCM process,SRAM-based TCAM,bit rate 1 Mbit/s,cell nonvolatile TCAM,cell size,clocked self-referenced sensing scheme,compact cells,fabricated nonvolatile TCAM,low voltage search operation,match delay,mushroom phase-change memory process,reliable search operation,size 90 nm,technology node,test chip design,two-bit encoding,Arrays,Clocks,Encoding,Microprocessors,Phase change materials,Sensors}, \ndoi={}, \nISSN={2158-5601}, \nmonth={June},\nabstract={This work demonstrates the first fabricated nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90nm CMOS technology and mushroom phase-change memory (PCM) process. To ensure reliable search operation with such compact cells, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding, and 2) a clocked self-referenced sensing scheme (CSRSS). The 1Mb chip demonstrates reliable low voltage search operation (VDDmin~750mV) and a match delay of 1.9 ns under nominal operating conditions.},\nnote = {(Acceptance Rate: 27\\%, 109 out of 396)}\n}\n\n\n","author_short":["Li, J.","Montoye, R.","Ishii, M.","Stawiasz, K.","Nishida, T.","Maloney, K.","Ditlow, G.","Lewis, S.","Maffitt, T.","Jordan, R.","others"],"key":"li2013vlsi","id":"li2013vlsi","bibbaseid":"li-montoye-ishii-stawiasz-nishida-maloney-ditlow-lewis-etal-1mb041m22t2rcellnonvolatiletcamwithtwobitencodingandclockedselfreferencedsensingstronghighlightpaperoftheyearstrong-2013","role":"author","urls":{},"keyword":["conference","CMOS memory circuits","SRAM chips","clocks","content-addressable storage","integrated circuit design","integrated circuit reliability","low-power electronics","phase change memories","search problems","2-transistor-2-resistive-storage cells","2T-2R cells","CSRSS","IBM CMOS technology","PCM process","SRAM-based TCAM","bit rate 1 Mbit/s","cell nonvolatile TCAM","cell size","clocked self-referenced sensing scheme","compact cells","fabricated nonvolatile TCAM","low voltage search operation","match delay","mushroom phase-change memory process","reliable search operation","size 90 nm","technology node","test chip design","two-bit encoding","Arrays","Clocks","Encoding","Microprocessors","Phase change materials","Sensors"],"metadata":{"authorlinks":{}},"html":""},"bibtype":"inproceedings","biburl":"http://www.seas.upenn.edu/~janeli/files/publications.bib","dataSources":["yLYmooEyKB3QB6BcW","5Z6JJjZhfwytLGvSE","A5c6eTvEQwuC3uBTF"],"keywords":["conference","cmos memory circuits","sram chips","clocks","content-addressable storage","integrated circuit design","integrated circuit reliability","low-power electronics","phase change memories","search problems","2-transistor-2-resistive-storage cells","2t-2r cells","csrss","ibm cmos technology","pcm process","sram-based tcam","bit rate 1 mbit/s","cell nonvolatile tcam","cell size","clocked self-referenced sensing scheme","compact cells","fabricated nonvolatile tcam","low voltage search operation","match delay","mushroom phase-change memory process","reliable search operation","size 90 nm","technology node","test chip design","two-bit encoding","arrays","clocks","encoding","microprocessors","phase change materials","sensors"],"search_terms":["1mb","cell","nonvolatile","tcam","two","bit","encoding","clocked","self","referenced","sensing","strong","highlight","paper","year","strong","li","montoye","ishii","stawiasz","nishida","maloney","ditlow","lewis","maffitt","jordan","others"],"title":"1Mb 0.41 $μ$m$^2$ 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (Highlight Paper of the Year)","year":2013}