3-D IC Interconnect Parasitic Capacitance Extraction With a Reformulated PGD Algorithm

3-D IC Interconnect Parasitic Capacitance Extraction With a Reformulated PGD Algorithm. Li, Y., Yan, S., Xu, X., Lyu, P., & Ren, Z. IEEE Transactions on Magnetics, 53(6):1–4, Institute of Electrical and Electronics Engineers (IEEE), June, 2017.
doi bibtex

@Article{         Li_2017ab,
  author        = {Li, Yalan and Yan, Shuai and Xu, Xiaoyu and Lyu, Pengfei and Ren, Zhuoxiang},
  citable       = {1},
  doi           = {10.1109/tmag.2017.2648852},
  file          = {Li_2017ab.pdf},
  group         = {casper},
  internal      = {0},
  issn          = {0018-9464},
  journal       = {IEEE Transactions on Magnetics},
  keywords      = {pgd,mor,electronics},
  language      = {english},
  month         = jun,
  number        = {6},
  pages         = {1--4},
  publisher     = {Institute of Electrical {and} Electronics Engineers ({IEEE})},
  title         = {{3-D} {IC} Interconnect Parasitic Capacitance Extraction With a Reformulated {PGD} Algorithm},
  volume        = {53},
  year          = {2017},
  shortjournal  = {IEEE Trans. Magn.}
}

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