A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. Lin, Y., Yang, C., Li, H., & Wang, C. M. In NVMSA, pages 1-6, 2015. IEEE.
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. [link]Link  A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. [link]Paper  bibtex   
@inproceedings{conf/nvmsa/LinYLW15,
  added-at = {2015-11-10T00:00:00.000+0100},
  author = {Lin, Ye-Jyun and Yang, Chia-Lin and Li, Hsiang-Pang and Wang, Cheng-Yuan Michael},
  biburl = {https://www.bibsonomy.org/bibtex/27f4021e877f9e8660a88ead6905f7e07/dblp},
  booktitle = {NVMSA},
  crossref = {conf/nvmsa/2015},
  ee = {http://dx.doi.org/10.1109/NVMSA.2015.7304363},
  interhash = {77bd55cd344b451005536a32cb658707},
  intrahash = {7f4021e877f9e8660a88ead6905f7e07},
  isbn = {978-1-4673-6688-5},
  keywords = {dblp},
  pages = {1-6},
  publisher = {IEEE},
  timestamp = {2015-11-11T11:36:56.000+0100},
  title = {A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.},
  url = {http://dblp.uni-trier.de/db/conf/nvmsa/nvmsa2015.html#LinYLW15},
  year = 2015
}

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