{"_id":"eDiHuwtFcTrAPHLmb","bibbaseid":"liu-chen-fan-zeng-afullmodefmevlsiarchitecturebasedon8x84x4adaptivehadamardtransformforqfhdh264avcencoder","authorIDs":[],"author_short":["Liu, J.","Chen, X.","Fan, Y.","Zeng, X."],"bibdata":{"bibtype":"article","type":"article","title":"A Full-mode FME VLSI Architecture Based on 8x8/4x4 Adaptive Hadamard Transform For QFHD H.264/AVC Encoder","abstract":"Adaptive Block-size Transform (ABT) has been added to H.264/AVC standard with the Fidelity Range Extension. In this paper, we apply this ABT concept to our FME design and propose a full-mode FME architecture based on 8x8/4x4 adaptive Hadamard Transform. This technique can avoid unifying all variable block-size blocks into 4x4-size blocks and improve the encoding performance. We also exploit the linearity of Hadamard Transform in quarter-pel refinement and decrease the cycles caused by the second long search process. In architecture level, we employ two interpolating engines that can support 8-pel and 4-pel input to time-share one SATD (Sum of Absolute Hadamard Transform) Generator. These strategies can increase parallelism and reduce the cycles efficiently. Besides, this design can support full modes, which guarantees the encoding performance. Experimental results show that our design can achieve real-time processing for QFHD@30fps at the operation frequency of 320MHz with 444.6K gates hardware.","language":"en","author":[{"propositions":[],"lastnames":["Liu"],"firstnames":["Jialiang"],"suffixes":[]},{"propositions":[],"lastnames":["Chen"],"firstnames":["Xinhua"],"suffixes":[]},{"propositions":[],"lastnames":["Fan"],"firstnames":["Yibo"],"suffixes":[]},{"propositions":[],"lastnames":["Zeng"],"firstnames":["Xiaoyang"],"suffixes":[]}],"keywords":"⛔ No DOI found","pages":"6","bibtex":"@article{liu_full-mode_nodate,\n\ttitle = {A {Full}-mode {FME} {VLSI} {Architecture} {Based} on 8x8/4x4 {Adaptive} {Hadamard} {Transform} {For} {QFHD} {H}.264/{AVC} {Encoder}},\n\tabstract = {Adaptive Block-size Transform (ABT) has been added to H.264/AVC standard with the Fidelity Range Extension. In this paper, we apply this ABT concept to our FME design and propose a full-mode FME architecture based on 8x8/4x4 adaptive Hadamard Transform. This technique can avoid unifying all variable block-size blocks into 4x4-size blocks and improve the encoding performance. We also exploit the linearity of Hadamard Transform in quarter-pel refinement and decrease the cycles caused by the second long search process. In architecture level, we employ two interpolating engines that can support 8-pel and 4-pel input to time-share one SATD (Sum of Absolute Hadamard Transform) Generator. These strategies can increase parallelism and reduce the cycles efficiently. Besides, this design can support full modes, which guarantees the encoding performance. Experimental results show that our design can achieve real-time processing for QFHD@30fps at the operation frequency of 320MHz with 444.6K gates hardware.},\n\tlanguage = {en},\n\tauthor = {Liu, Jialiang and Chen, Xinhua and Fan, Yibo and Zeng, Xiaoyang},\n\tkeywords = {⛔ No DOI found},\n\tpages = {6}\n}\n\n","author_short":["Liu, J.","Chen, X.","Fan, Y.","Zeng, X."],"key":"liu_full-mode_nodate","id":"liu_full-mode_nodate","bibbaseid":"liu-chen-fan-zeng-afullmodefmevlsiarchitecturebasedon8x84x4adaptivehadamardtransformforqfhdh264avcencoder","role":"author","urls":{},"keyword":["⛔ No DOI found"],"downloads":0},"bibtype":"article","biburl":"https://bibbase.org/zotero/ky25","creationDate":"2019-05-11T17:47:04.192Z","downloads":0,"keywords":["⛔ no doi found"],"search_terms":["full","mode","fme","vlsi","architecture","based","8x8","4x4","adaptive","hadamard","transform","qfhd","264","avc","encoder","liu","chen","fan","zeng"],"title":"A Full-mode FME VLSI Architecture Based on 8x8/4x4 Adaptive Hadamard Transform For QFHD H.264/AVC Encoder","year":null,"dataSources":["XxiQtwZYfozhQmvGR"]}