@inproceedings{
 title = {Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture},
 type = {inproceedings},
 year = {2018},
 pages = {199–208},
 websites = {http://arxiv.org/abs/1708.04701},
 publisher = {Institute of Electrical and Electronics Engineers Inc.},
 id = {b3933d22-d9f1-354a-b19d-b88c96edc1e5},
 created = {2019-10-01T17:20:54.687Z},
 file_attached = {false},
 profile_id = {42d295c0-0737-38d6-8b43-508cab6ea85d},
 last_modified = {2020-05-11T14:43:33.021Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Liu2018},
 private_publication = {false},
 abstract = {Intel Xeon Phi many-integrated-core (MIC) architectures usher in a new era of terascale integration. Among emerging killer applications, parallel graph processing has been a critical technique to analyze connected data. In this paper, we empirically evaluate various computing platforms including an Intel Xeon E5 CPU, a Nvidia Geforce GTX1070 GPU and an Xeon Phi 7210 processor codenamed Knights Landing (KNL) in the domain of parallel graph processing. We show that the KNL gains encouraging performance when processing graphs, so that it can become a promising solution to accelerating multi-threaded graph applications. We further characterize the impact of KNL architectural enhancements on the performance of a state-of-the art graph framework.We have four key observations: 1 Different graph applications require distinctive numbers of threads to reach the peak performance. For the same application, various datasets need even different numbers of threads to achieve the best performance. 2 Only a few graph applications benefit from the high bandwidth MCDRAM, while others favor the low latency DDR4 DRAM. 3 Vector processing units executing AVX512 SIMD instructions on KNLs are underutilized when running the state-of-the-art graph framework. 4 The sub-NUMA cache clustering mode offering the lowest local memory access latency hurts the performance of graph benchmarks that are lack of NUMA awareness. At last, We suggest future works including system auto-tuning tools and graph framework optimizations to fully exploit the potential of KNL for parallel graph processing.},
 bibtype = {inproceedings},
 author = {Liu, Xu and Chen, Langshi and Firoz, Jesun S. and Qiu, Judy and Jiang, Lei},
 doi = {10.1109/ISPASS.2018.00033},
 booktitle = {2018 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2018}
}

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For the same application, various datasets need even different numbers of threads to achieve the best performance. 2 Only a few graph applications benefit from the high bandwidth MCDRAM, while others favor the low latency DDR4 DRAM. 3 Vector processing units executing AVX512 SIMD instructions on KNLs are underutilized when running the state-of-the-art graph framework. 4 The sub-NUMA cache clustering mode offering the lowest local memory access latency hurts the performance of graph benchmarks that are lack of NUMA awareness. At last, We suggest future works including system auto-tuning tools and graph framework optimizations to fully exploit the potential of KNL for parallel graph processing.","bibtype":"inproceedings","author":"Liu, Xu and Chen, Langshi and Firoz, Jesun S. and Qiu, Judy and Jiang, Lei","doi":"10.1109/ISPASS.2018.00033","booktitle":"2018 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2018","bibtex":"@inproceedings{\n title = {Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture},\n type = {inproceedings},\n year = {2018},\n pages = {199–208},\n websites = {http://arxiv.org/abs/1708.04701},\n publisher = {Institute of Electrical and Electronics Engineers Inc.},\n id = {b3933d22-d9f1-354a-b19d-b88c96edc1e5},\n created = {2019-10-01T17:20:54.687Z},\n file_attached = {false},\n profile_id = {42d295c0-0737-38d6-8b43-508cab6ea85d},\n last_modified = {2020-05-11T14:43:33.021Z},\n read = {false},\n starred = {false},\n authored = {true},\n confirmed = {true},\n hidden = {false},\n citation_key = {Liu2018},\n private_publication = {false},\n abstract = {Intel Xeon Phi many-integrated-core (MIC) architectures usher in a new era of terascale integration. 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For the same application, various datasets need even different numbers of threads to achieve the best performance. 2 Only a few graph applications benefit from the high bandwidth MCDRAM, while others favor the low latency DDR4 DRAM. 3 Vector processing units executing AVX512 SIMD instructions on KNLs are underutilized when running the state-of-the-art graph framework. 4 The sub-NUMA cache clustering mode offering the lowest local memory access latency hurts the performance of graph benchmarks that are lack of NUMA awareness. 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