Future challenges of flash memory technologies. Lu, C. Y., Hsieh, K. Y., & Liu, R. Microelectronic Engineering, 86(3):283–286, March, 2009. doi abstract bibtex Flash memory application has seen explosive growth in recent years and this trend is likely to continue because new and more demanding applications are constantly added partly due to the need for low power solid-state storage and partly due to rapidly declining prices. Conventional floating gate flash memories, no matter in NOR or NAND architecture, however, face steep challenges. For NOR flash, the junction breakdown and short channel effects have essentially squeezed out the device design space below 45 nm node. For NAND flash, the tight spacing, floating gate interference and the need for sufficient gate control (gate coupling ratio) have also ruled out the continuation of the conventional floating gate device below approximately 32 nm node. Charge trapping devices, exploiting high-K inter-poly dielectric (IPD) or by innovative tunneling barrier engineering, are proposed to continue scaling flash memories. Eventually, when too few electrons are stored and the logic level retention becomes smeared by statistical fluctuation over the life time of the device, 3-D layering of devices may provide the ultimate solution. © 2008 Elsevier B.V. All rights reserved.
@article{lu_future_2009,
title = {Future challenges of flash memory technologies},
volume = {86},
issn = {01679317},
doi = {10.1016/j.mee.2008.08.007},
abstract = {Flash memory application has seen explosive growth in recent years and this trend is likely to continue because new and more demanding applications are constantly added partly due to the need for low power solid-state storage and partly due to rapidly declining prices. Conventional floating gate flash memories, no matter in NOR or NAND architecture, however, face steep challenges. For NOR flash, the junction breakdown and short channel effects have essentially squeezed out the device design space below 45 nm node. For NAND flash, the tight spacing, floating gate interference and the need for sufficient gate control (gate coupling ratio) have also ruled out the continuation of the conventional floating gate device below approximately 32 nm node. Charge trapping devices, exploiting high-K inter-poly dielectric (IPD) or by innovative tunneling barrier engineering, are proposed to continue scaling flash memories. Eventually, when too few electrons are stored and the logic level retention becomes smeared by statistical fluctuation over the life time of the device, 3-D layering of devices may provide the ultimate solution. © 2008 Elsevier B.V. All rights reserved.},
number = {3},
urldate = {2020-01-19},
journal = {Microelectronic Engineering},
author = {Lu, Chih Yuan and Hsieh, Kuang Yeu and Liu, Rich},
month = mar,
year = {2009},
keywords = {Band-to-band tunneling hot hole, Bandgap engineered SONOS, Channel hot electron, Charge trapping device, Flash memory, Floating gate, NAND, NOR},
pages = {283--286},
}
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