1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks. Lu, S., Zhang, Z., & Papaefthymiou, M. In 2015 Symposium on VLSI Circuits (VLSI Circuits), pages C246–C247, June, 2015. doi abstract bibtex A 128-bit Advanced Encryption Standard (AES) core targeted for high-performance security applications is fabricated in a 65nm CMOS technology. A novel charge-recovery logic family, called Bridge Boost Logic (BBL), is introduced in this design to achieve switching-independent energy dissipation for an intrinsic high resistance against Differential Power Analysis (DPA) attacks. Based on measurements, the AES core achieves a throughput of 16.90Gbps and power consumption of 98mW, exhibiting 720× higher DPA resistance and 30% lower power than its conventional CMOS counterpart at the same clock frequency.
@inproceedings{lu_1.32ghz_2015,
title = {1.32GHz high-throughput charge-recovery {AES} core with resistance to {DPA} attacks},
doi = {10.1109/VLSIC.2015.7231274},
abstract = {A 128-bit Advanced Encryption Standard (AES) core targeted for high-performance security applications is fabricated in a 65nm CMOS technology. A novel charge-recovery logic family, called Bridge Boost Logic (BBL), is introduced in this design to achieve switching-independent energy dissipation for an intrinsic high resistance against Differential Power Analysis (DPA) attacks. Based on measurements, the AES core achieves a throughput of 16.90Gbps and power consumption of 98mW, exhibiting 720× higher DPA resistance and 30\% lower power than its conventional CMOS counterpart at the same clock frequency.},
booktitle = {2015 {Symposium} on {VLSI} {Circuits} ({VLSI} {Circuits})},
author = {Lu, S. and Zhang, Z. and Papaefthymiou, M.},
month = jun,
year = {2015},
pages = {C246--C247}
}
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