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Quantum Approximate Optimization Algorithm (QAOA) is studied primarily to find approximate solutions to combinatorial optimization problems. For a graph with $n$ vertices and $m$ edges, a depth $p$ QAOA for the Max-cut problem requires $2{\}cdot m {\}cdot p$ CNOT gates. CNOT is one of the primary sources of error in modern quantum computers. In this paper, we propose two hardware independent methods to reduce the number of CNOT gates in the circuit. First, we present a method based on Edge Coloring of the input graph that minimizes the the number of cycles (termed as depth of the circuit), and reduces upto ${\}lfloor {\}frac\{n\}\{2\} {\}rfloor$ CNOT gates. Next, we depict another method based on Depth First Search (DFS) on the input graph that reduces $n-1$ CNOT gates, but increases depth of the circuit moderately. We analytically derive the condition for which the reduction in CNOT gates overshadows this increase in depth, and the error probability of the circuit is still lowered. We show that all IBM Quantum Hardware satisfy this condition. We simulate these two methods for graphs of various sparsity with the \textit\ibmq\_manhattan\ noise model, and show that the DFS based method outperforms the edge coloring based method, which in turn, outperforms the traditional QAOA circuit in terms of reduction in the number of CNOT gates, and hence the probability of error of the circuit.

@article{majumdar_optimizing_2021, title = {Optimizing {Ansatz} {Design} in {QAOA} for {Max}-cut}, url = {http://arxiv.org/abs/2106.02812}, abstract = {Quantum Approximate Optimization Algorithm (QAOA) is studied primarily to find approximate solutions to combinatorial optimization problems. For a graph with \$n\$ vertices and \$m\$ edges, a depth \$p\$ QAOA for the Max-cut problem requires \$2{\textbackslash}cdot m {\textbackslash}cdot p\$ CNOT gates. CNOT is one of the primary sources of error in modern quantum computers. In this paper, we propose two hardware independent methods to reduce the number of CNOT gates in the circuit. First, we present a method based on Edge Coloring of the input graph that minimizes the the number of cycles (termed as depth of the circuit), and reduces upto \${\textbackslash}lfloor {\textbackslash}frac\{n\}\{2\} {\textbackslash}rfloor\$ CNOT gates. Next, we depict another method based on Depth First Search (DFS) on the input graph that reduces \$n-1\$ CNOT gates, but increases depth of the circuit moderately. We analytically derive the condition for which the reduction in CNOT gates overshadows this increase in depth, and the error probability of the circuit is still lowered. We show that all IBM Quantum Hardware satisfy this condition. We simulate these two methods for graphs of various sparsity with the {\textbackslash}textit\{ibmq{\textbackslash}\_manhattan\} noise model, and show that the DFS based method outperforms the edge coloring based method, which in turn, outperforms the traditional QAOA circuit in terms of reduction in the number of CNOT gates, and hence the probability of error of the circuit.}, urldate = {2022-05-23}, journal = {arXiv:2106.02812 [quant-ph]}, author = {Majumdar, Ritajit and Madan, Dhiraj and Bhoumik, Debasmita and Vinayagamurthy, Dhinakaran and Raghunathan, Shesha and Sur-Kolay, Susmita}, month = jun, year = {2021}, note = {arXiv: 2106.02812}, keywords = {Computer Science - Data Structures and Algorithms, Quantum Physics}, }

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