Timing analysis of asynchronous circuits using timed automata. Maler, O. & Pnueli, A. In Proceedings of Correct Hardware Design and Verification Methods (CHARME), pages 189-205, 1995. ![Timing analysis of asynchronous circuits using timed automata [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper bibtex @inproceedings{ dblp4253534,
title = {Timing analysis of asynchronous circuits using timed automata},
author = {Oded Maler and Amir Pnueli},
author_short = {Maler, O. and Pnueli, A.},
bibtype = {inproceedings},
type = {inproceedings},
year = {1995},
key = {dblp4253534},
id = {dblp4253534},
biburl = {http://www.dblp.org/rec/bibtex/conf/charme/MalerP95},
url = {http://dx.doi.org/10.1007/3-540-60385-9_12},
conference = {CHARME},
pages = {189-205},
text = {CHARME 1995:189-205},
booktitle = {Proceedings of Correct Hardware Design and Verification Methods (CHARME)}
}
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{"_id":"dRhhqHxgScrAZFgTX","bibbaseid":"maler-pnueli-timinganalysisofasynchronouscircuitsusingtimedautomata-1995","downloads":0,"creationDate":"2015-07-05T11:05:40.288Z","title":"Timing analysis of asynchronous circuits using timed automata","author_short":["Maler, O.","Pnueli, A."],"year":1995,"bibtype":"inproceedings","biburl":"http://www.dblp.org/rec/bibtex/conf/charme/MalerP95","bibdata":{"title":"Timing analysis of asynchronous circuits using timed automata","author":["Oded Maler","Amir Pnueli"],"author_short":["Maler, O.","Pnueli, A."],"bibtype":"inproceedings","type":"inproceedings","year":"1995","key":"dblp4253534","id":"dblp4253534","biburl":"http://www.dblp.org/rec/bibtex/conf/charme/MalerP95","url":"http://dx.doi.org/10.1007/3-540-60385-9_12","conference":"CHARME","pages":"189-205","text":"CHARME 1995:189-205","booktitle":"Proceedings of Correct Hardware Design and Verification Methods (CHARME)","bibtex":"@inproceedings{ dblp4253534,\n title = {Timing analysis of asynchronous circuits using timed automata},\n author = {Oded Maler and Amir Pnueli},\n author_short = {Maler, O. and Pnueli, A.},\n bibtype = {inproceedings},\n type = {inproceedings},\n year = {1995},\n key = {dblp4253534},\n id = {dblp4253534},\n biburl = {http://www.dblp.org/rec/bibtex/conf/charme/MalerP95},\n url = {http://dx.doi.org/10.1007/3-540-60385-9_12},\n conference = {CHARME},\n pages = {189-205},\n text = {CHARME 1995:189-205},\n booktitle = {Proceedings of Correct Hardware Design and Verification Methods (CHARME)}\n}","bibbaseid":"maler-pnueli-timinganalysisofasynchronouscircuitsusingtimedautomata-1995","role":"author","urls":{"Paper":"http://dx.doi.org/10.1007/3-540-60385-9_12"},"downloads":0},"search_terms":["timing","analysis","asynchronous","circuits","using","timed","automata","maler","pnueli"],"keywords":[],"authorIDs":[],"dataSources":["eS9TDFvYGkF7ZwYc6"]}