Anytime system level verification via parallel random exhaustive hardware in the loop simulation. Mancini, T., Mari, F., Massini, A., Melatti, I., & Tronci, E. Microprocessors and Microsystems, 41:12-28, Elsevier, 2016. cited By 0
Anytime system level verification via parallel random exhaustive hardware in the loop simulation [link]Paper  doi  abstract   bibtex   
System level verification of cyber-physical systems has the goal of verifying that the whole (i.e., software + hardware) system meets the given specifications. Model checkers for hybrid systems cannot handle system level verification of actual systems. Thus, Hardware In the Loop Simulation (HILS) is currently the main workhorse for system level verification. By using model checking driven exhaustive HILS, System Level Formal Verification (SLFV) can be effectively carried out for actual systems. We present a parallel random exhaustive HILS based model checker for hybrid systems that, by simulating all operational scenarios exactly once in a uniform random order, is able to provide, at any time during the verification process, an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-be-simulated scenario (Omission Probability). We show effectiveness of the proposed approach by presenting experimental results on SLFV of the Inverted Pendulum on a Cart and the Fuel Control System examples in the Simulink distribution. To the best of our knowledge, no previously published model checker can exhaustively verify hybrid systems of such a size and provide at any time an upper bound to the Omission Probability. © 2015 Elsevier B.V. All rights reserved.
@ARTICLE{Mancini201612,
author={Mancini, T. and Mari, F. and Massini, A. and Melatti, I. and Tronci, E.},
title={Anytime system level verification via parallel random exhaustive hardware in the loop simulation},
journal={Microprocessors and Microsystems},
year={2016},
volume={41},
pages={12-28},
doi={10.1016/j.micpro.2015.10.010},
note={cited By 0},
url={https://www.scopus.com/inward/record.uri?eid=2-s2.0-84954475986&partnerID=40&md5=aaa59999ee06a15ae71fdc764dee32c1},
affiliation={Computer Science Department, Sapienza University of Rome, Italy},
abstract={System level verification of cyber-physical systems has the goal of verifying that the whole (i.e., software + hardware) system meets the given specifications. Model checkers for hybrid systems cannot handle system level verification of actual systems. Thus, Hardware In the Loop Simulation (HILS) is currently the main workhorse for system level verification. By using model checking driven exhaustive HILS, System Level Formal Verification (SLFV) can be effectively carried out for actual systems. We present a parallel random exhaustive HILS based model checker for hybrid systems that, by simulating all operational scenarios exactly once in a uniform random order, is able to provide, at any time during the verification process, an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-be-simulated scenario (Omission Probability). We show effectiveness of the proposed approach by presenting experimental results on SLFV of the Inverted Pendulum on a Cart and the Fuel Control System examples in the Simulink distribution. To the best of our knowledge, no previously published model checker can exhaustively verify hybrid systems of such a size and provide at any time an upper bound to the Omission Probability. © 2015 Elsevier B.V. All rights reserved.},
author_keywords={Hardware in the loop simulation;  Model checking driven simulation;  Model Checking of Hybrid Systems},
keywords={Embedded systems;  Formal verification;  Hardware;  Hybrid systems;  Probability;  Reconfigurable hardware;  Synthetic apertures;  Traction (friction);  Verification, Actual system;  Anytime systems;  Cyber physical systems (CPSs);  Hardware in-the-loop simulation;  Inverted pendulum;  Model checker;  Operational scenario;  Verification process, Model checking},
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correspondence_address1={Mancini, T.; Computer Science Department, Sapienza University of RomeItaly; email: tmancini@di.uniroma1.it},
publisher={Elsevier},
issn={01419331},
coden={MIMID},
language={English},
abbrev_source_title={Microprocessors Microsyst},
document_type={Article},
source={Scopus},
}
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