Qualifying Relative Timing Constraints for Asynchronous Circuits. Manoranjan, J. V. & Stevens, K. S. In 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016, Porto Alegre, Brazil, May 8-11, 2016, pages 91–98, 2016.
Paper doi bibtex @inproceedings{DBLP:conf/async/ManoranjanS16,
author = {Jotham Vaddaboina Manoranjan and
Kenneth S. Stevens},
title = {Qualifying Relative Timing Constraints for Asynchronous Circuits},
booktitle = {22nd {IEEE} International Symposium on Asynchronous Circuits and Systems,
{ASYNC} 2016, Porto Alegre, Brazil, May 8-11, 2016},
pages = {91--98},
year = {2016},
crossref = {DBLP:conf/async/2016},
url = {https://doi.org/10.1109/ASYNC.2016.23},
doi = {10.1109/ASYNC.2016.23},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/bib/conf/async/ManoranjanS16},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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