Design environment for hardware generation of SLFF neural network topologies with ELM training capability. Martínez-Villena, J. M.; Francés-Víllora, J. V.; Muñoz, A. R.; Bataller-Mompeán, M.; Guerrero-Martínez, J.; Wegrzyn, M.; and Adamski, M. In 13th IEEE International Conference on Industrial Informatics, INDIN 2015, Cambridge, United Kingdom, July 22-24, 2015, pages 868–875, 2015. IEEE.
Paper doi bibtex @inproceedings{DBLP:conf/indin/Martinez-Villena15,
author = {Jos{\'{e}} Miguel Mart{\'{\i}}nez{-}Villena and
Jos{\'{e}} Vicente Franc{\'{e}}s{-}V{\'{\i}}llora and
Alfredo Rosado Mu{\~{n}}oz and
Manuel Bataller{-}Mompe{\'{a}}n and
Juan{-}Francisco Guerrero{-}Mart{\'{\i}}nez and
Marek Wegrzyn and
Marian Adamski},
title = {Design environment for hardware generation of {SLFF} neural network
topologies with {ELM} training capability},
booktitle = {13th {IEEE} International Conference on Industrial Informatics, {INDIN}
2015, Cambridge, United Kingdom, July 22-24, 2015},
pages = {868--875},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/INDIN.2015.7281850},
doi = {10.1109/INDIN.2015.7281850},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/indin/Martinez-Villena15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}