{"_id":"6mXGNauh2eXEhRdjK","bibbaseid":"mazouz-touati-barthou-performanceevaluationandanalysisofthreadpinningstrategiesonmulticoreplatformscasestudyofspecompapplicationsonintelarchitectures-2011","authorIDs":["gH8cyowDfvmpgEymM"],"author_short":["Mazouz, A.","Touati, S. A. A.","Barthou, D."],"bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"firstnames":["Abdelhafid"],"propositions":[],"lastnames":["Mazouz"],"suffixes":[]},{"firstnames":["Sid","Ahmed","Ali"],"propositions":[],"lastnames":["Touati"],"suffixes":[]},{"firstnames":["Denis"],"propositions":[],"lastnames":["Barthou"],"suffixes":[]}],"editor":[{"firstnames":["Waleed","W."],"propositions":[],"lastnames":["Smari"],"suffixes":[]},{"firstnames":["John","P."],"propositions":[],"lastnames":["McIntire"],"suffixes":[]}],"title":"Performance evaluation and analysis of thread pinning strategies on multi-core platforms: Case study of SPEC OMP applications on intel architectures","booktitle":"2011 International Conference on High Performance Computing & Simulation, HPCS 2012, Istanbul, Turkey, July 4-8, 2011","pages":"273–279","publisher":"IEEE","year":"2011","url":"https://doi.org/10.1109/HPCSim.2011.5999834","doi":"10.1109/HPCSIM.2011.5999834","timestamp":"Sun, 06 Oct 2024 01:00:00 +0200","biburl":"https://dblp.org/rec/conf/ieeehpcs/MazouzTB11.bib","bibsource":"dblp computer science bibliography, https://dblp.org","bibtex":"@inproceedings{DBLP:conf/ieeehpcs/MazouzTB11,\n author = {Abdelhafid Mazouz and\n Sid Ahmed Ali Touati and\n Denis Barthou},\n editor = {Waleed W. Smari and\n John P. McIntire},\n title = {Performance evaluation and analysis of thread pinning strategies on\n multi-core platforms: Case study of {SPEC} {OMP} applications on intel\n architectures},\n booktitle = {2011 International Conference on High Performance Computing {\\&} Simulation,\n {HPCS} 2012, Istanbul, Turkey, July 4-8, 2011},\n pages = {273--279},\n publisher = {{IEEE}},\n year = {2011},\n url = {https://doi.org/10.1109/HPCSim.2011.5999834},\n doi = {10.1109/HPCSIM.2011.5999834},\n timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},\n biburl = {https://dblp.org/rec/conf/ieeehpcs/MazouzTB11.bib},\n bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n","author_short":["Mazouz, A.","Touati, S. A. A.","Barthou, D."],"editor_short":["Smari, W. W.","McIntire, J. P."],"key":"DBLP:conf/ieeehpcs/MazouzTB11","id":"DBLP:conf/ieeehpcs/MazouzTB11","bibbaseid":"mazouz-touati-barthou-performanceevaluationandanalysisofthreadpinningstrategiesonmulticoreplatformscasestudyofspecompapplicationsonintelarchitectures-2011","role":"author","urls":{"Paper":"https://doi.org/10.1109/HPCSim.2011.5999834"},"metadata":{"authorlinks":{"barthou, d":"https://bibbase.org/show?bib=https://dblp.org/pid/66/2364.bib"}},"downloads":0},"bibtype":"inproceedings","biburl":"https://dblp.org/pid/66/2364.bib","creationDate":"2020-09-28T15:09:27.248Z","downloads":0,"keywords":[],"search_terms":["performance","evaluation","analysis","thread","pinning","strategies","multi","core","platforms","case","study","spec","omp","applications","intel","architectures","mazouz","touati","barthou"],"title":"Performance evaluation and analysis of thread pinning strategies on multi-core platforms: Case study of SPEC OMP applications on intel architectures","year":2011,"dataSources":["QzYnA59epiHCud8Xh"]}