In *2008 International Conference on Application-Specific Systems, Architectures and Processors*, pages 43–48, July, 2008.

doi abstract bibtex

doi abstract bibtex

Fully-pipelined simple modular structures are presented in this paper for efficient hardware realization of discrete Hadamard transform (HT). From the kernel matrix of HT, we have derived four different pipelined modular designs for transform length N = 4. It is shown further that the HT of transform-length N = 8 can be obtained from two 4-point HT modules, and similarly, the HT of transform-length N=16 can be obtained from four 4-point HT modules. Long-length transforms may, however, be computed from these short-length modules as N-point transforms can be computed from 2M number of M point HT-modules, where M = N$^{\textrm{1/2}}$. The proposed architectures are coded in VHDL, simulated by Xilinx ISE tool for validation and testing; and synthesized thereafter to be implemented in different FPGA devices, e.g., Virtex-E, Virtex-II Pro and Virtex-4. From the synthesis result, it is found that the proposed designs involve considerably less number of slices and provide significantly higher best-achievable-frequency compared with the existing architectures for FPGA implementation of HT.

@inproceedings{meher_fully-pipelined_2008, title = {Fully-pipelined efficient architectures for {FPGA} realization of discrete {Hadamard} transform}, doi = {10.1109/ASAP.2008.4580152}, abstract = {Fully-pipelined simple modular structures are presented in this paper for efficient hardware realization of discrete Hadamard transform (HT). From the kernel matrix of HT, we have derived four different pipelined modular designs for transform length N = 4. It is shown further that the HT of transform-length N = 8 can be obtained from two 4-point HT modules, and similarly, the HT of transform-length N=16 can be obtained from four 4-point HT modules. Long-length transforms may, however, be computed from these short-length modules as N-point transforms can be computed from 2M number of M point HT-modules, where M = N$^{\textrm{1/2}}$. The proposed architectures are coded in VHDL, simulated by Xilinx ISE tool for validation and testing; and synthesized thereafter to be implemented in different FPGA devices, e.g., Virtex-E, Virtex-II Pro and Virtex-4. From the synthesis result, it is found that the proposed designs involve considerably less number of slices and provide significantly higher best-achievable-frequency compared with the existing architectures for FPGA implementation of HT.}, booktitle = {2008 {International} {Conference} on {Application}-{Specific} {Systems}, {Architectures} and {Processors}}, author = {Meher, P. K. and Patra, J. C.}, month = jul, year = {2008}, pages = {43--48} }

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