Stochastic cycle period analysis in timed circuits

Stochastic cycle period analysis in timed circuits. Mercer, E. G. & Myers, C. J. In IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pages 172–175, 2000.

Paper doi bibtex

@inproceedings{DBLP:conf/iscas/MercerM00,
  author    = {Eric G. Mercer and
               Chris J. Myers},
  title     = {Stochastic cycle period analysis in timed circuits},
  booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
               Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
               May 2000, Proceedings},
  pages     = {172--175},
  year      = {2000},
  crossref  = {DBLP:conf/iscas/2000},
  url       = {https://doi.org/10.1109/ISCAS.2000.856286},
  doi       = {10.1109/ISCAS.2000.856286},
  timestamp = {Sun, 22 Oct 2017 13:09:25 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/MercerM00},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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