Modular Synthesis of Timed Circuits using Partial Order Reduction

Modular Synthesis of Timed Circuits using Partial Order Reduction. Mercer, E., Myers, C. J., & Yoneda, T. Electr. Notes Theor. Comput. Sci., 65(6):180–201, 2002.

Paper doi bibtex

@article{DBLP:journals/entcs/MercerMY02,
  author    = {Eric Mercer and
               Chris J. Myers and
               Tomohiro Yoneda},
  title     = {Modular Synthesis of Timed Circuits using Partial Order Reduction},
  journal   = {Electr. Notes Theor. Comput. Sci.},
  volume    = {65},
  number    = {6},
  pages     = {180--201},
  year      = {2002},
  url       = {https://doi.org/10.1016/S1571-0661(04)80476-6},
  doi       = {10.1016/S1571-0661(04)80476-6},
  timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/entcs/MercerMY02},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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{"_id":"Mt8uJfeaDCh2mQFqt","bibbaseid":"mercer-myers-yoneda-modularsynthesisoftimedcircuitsusingpartialorderreduction-2002","authorIDs":[],"author_short":["Mercer, E.","Myers, C. J.","Yoneda, T."],"bibdata":{"bibtype":"article","type":"article","author":[{"firstnames":["Eric"],"propositions":[],"lastnames":["Mercer"],"suffixes":[]},{"firstnames":["Chris","J."],"propositions":[],"lastnames":["Myers"],"suffixes":[]},{"firstnames":["Tomohiro"],"propositions":[],"lastnames":["Yoneda"],"suffixes":[]}],"title":"Modular Synthesis of Timed Circuits using Partial Order Reduction","journal":"Electr. Notes Theor. Comput. Sci.","volume":"65","number":"6","pages":"180–201","year":"2002","url":"https://doi.org/10.1016/S1571-0661(04)80476-6","doi":"10.1016/S1571-0661(04)80476-6","timestamp":"Sun, 02 Jun 2019 01:00:00 +0200","biburl":"https://dblp.org/rec/bib/journals/entcs/MercerMY02","bibsource":"dblp computer science bibliography, https://dblp.org","bibtex":"@article{DBLP:journals/entcs/MercerMY02,\n author = {Eric Mercer and\n Chris J. Myers and\n Tomohiro Yoneda},\n title = {Modular Synthesis of Timed Circuits using Partial Order Reduction},\n journal = {Electr. Notes Theor. Comput. Sci.},\n volume = {65},\n number = {6},\n pages = {180--201},\n year = {2002},\n url = {https://doi.org/10.1016/S1571-0661(04)80476-6},\n doi = {10.1016/S1571-0661(04)80476-6},\n timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},\n biburl = {https://dblp.org/rec/bib/journals/entcs/MercerMY02},\n bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n","author_short":["Mercer, E.","Myers, C. J.","Yoneda, T."],"key":"DBLP:journals/entcs/MercerMY02","id":"DBLP:journals/entcs/MercerMY02","bibbaseid":"mercer-myers-yoneda-modularsynthesisoftimedcircuitsusingpartialorderreduction-2002","role":"author","urls":{"Paper":"https://doi.org/10.1016/S1571-0661(04)80476-6"},"downloads":0,"html":""},"bibtype":"article","biburl":"https://ycunxi.github.io/utah-csl/bibtex/all.bib","creationDate":"2019-11-14T21:37:03.892Z","downloads":0,"keywords":[],"search_terms":["modular","synthesis","timed","circuits","using","partial","order","reduction","mercer","myers","yoneda"],"title":"Modular Synthesis of Timed Circuits using Partial Order Reduction","year":2002,"dataSources":["L6BLFSB28hKk5Nt67"]}