A case for small row buffers in non-volatile main memories

A case for small row buffers in non-volatile main memories. Meza, J., Li, J., & Mutlu, O. In 2012 IEEE 30th International Conference on Computer Design (<strong>ICCD</strong>), pages 484–485, Sept, 2012. (Acceptance rate: 25%, 61 out of 241)
doi abstract bibtex

DRAM-based main memories have read operations that destroy the read data, and as a result, must buffer large amounts of data on each array access to keep chip costs low. Unfortunately, system-level trends such as increased memory contention in multi-core architectures and data mapping schemes that improve memory parallelism lead to only a small amount of the buffered data to be accessed. This makes buffering large amounts of data on every memory array access energy-inefficient; yet organizing DRAM chips to buffer small amounts of data is costly, as others have shown. Emerging non-volatile memories (NVMs) such as PCM, STT-RAM, and RRAM, however, do not have destructive read operations, opening up opportunities for employing small row buffers without incurring additional area penalty and/or design complexity. In this work, we discuss and evaluate architectural changes to enable small row buffers at a low cost in NVMs. We find that on a multi-core system, reducing the row buffer size can greatly reduce main memory dynamic energy compared to a DRAM baseline with large row sizes, without greatly affecting endurance, and for some NVM technologies, leads to improved performance.

@INPROCEEDINGS{meza2012iccd, 
author={Justin Meza and Jing Li and Onur Mutlu}, 
booktitle={2012 IEEE 30th International Conference on Computer Design (<strong>ICCD</strong>)}, 
title={A case for small row buffers in non-volatile main memories}, 
year={2012},
date={2012-09-30},
volume={}, 
number={}, 
pages={484--485}, 
keywords={conference, DRAM chips,buffer circuits,multiprocessing systems,DRAM baseline,DRAM chips,DRAM-based main memories,NVM technologies,array access,buffered data,chip costs,data mapping schemes,main memory dynamic energy,memory array access,memory parallelism,multicore architectures,nonvolatile main memories,read operations,row buffer size,small row buffers,system-level trends,Arrays,Memory management,Nonvolatile memory,Organizations,Phase change materials,Random access memory}, 
abstract={DRAM-based main memories have read operations that destroy the read data, and as a result, must buffer large amounts of data on each array access to keep chip costs low. Unfortunately, system-level trends such as increased memory contention in multi-core architectures and data mapping schemes that improve memory parallelism lead to only a small amount of the buffered data to be accessed. This makes buffering large amounts of data on every memory array access energy-inefficient; yet organizing DRAM chips to buffer small amounts of data is costly, as others have shown. Emerging non-volatile memories (NVMs) such as PCM, STT-RAM, and RRAM, however, do not have destructive read operations, opening up opportunities for employing small row buffers without incurring additional area penalty and/or design complexity. In this work, we discuss and evaluate architectural changes to enable small row buffers at a low cost in NVMs. We find that on a multi-core system, reducing the row buffer size can greatly reduce main memory dynamic energy compared to a DRAM baseline with large row sizes, without greatly affecting endurance, and for some NVM technologies, leads to improved performance.},
doi={10.1109/ICCD.2012.6378685}, 
ISSN={1063-6404}, 
month={Sept},
note={(Acceptance rate: <u>25\%</u>, 61 out of 241)},
}

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