A graph placement methodology for fast chip design. Mirhoseini, A., Goldie, A., Yazgan, M., Jiang, J. W., Songhori, E. M., Wang, S., Lee, Y., Johnson, E., Pathak, O., Nazi, A., Pak, J., Tong, A., Srinivasa, K., Hang, W., Tuncer, E., Le, Q. V., Laudon, J., Ho, R., Carpenter, R., & Dean, J. Nat., 594(7862):207–212, 2021. Paper doi bibtex @article{DBLP:journals/nature/MirhoseiniGYJSW21,
author = {Azalia Mirhoseini and
Anna Goldie and
Mustafa Yazgan and
Joe Wenjie Jiang and
Ebrahim M. Songhori and
Shen Wang and
Young{-}Joon Lee and
Eric Johnson and
Omkar Pathak and
Azade Nazi and
Jiwoo Pak and
Andy Tong and
Kavya Srinivasa and
William Hang and
Emre Tuncer and
Quoc V. Le and
James Laudon and
Richard Ho and
Roger Carpenter and
Jeff Dean},
title = {A graph placement methodology for fast chip design},
journal = {Nat.},
volume = {594},
number = {7862},
pages = {207--212},
year = {2021},
url = {https://doi.org/10.1038/s41586-021-03544-w},
doi = {10.1038/S41586-021-03544-W},
timestamp = {Mon, 05 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/nature/MirhoseiniGYJSW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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