Design Methodologies for Yield Enhancement and Power Efficiency in SRAM-Based SoCs. Mohammad, B.; Saleh, H.; and Ismail, M. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015.
abstract   bibtex   
© 2015 IEEE. This paper comprises two new methodologies to improve yield and reduce system-on-a-chip power. The first methodology is based on faulty static random-access memory (SRAM) cells detections and cache resizing. The key advantage of this approach is that it enables the end user to control the system's parameters to be error tolerant. Furthermore, this technique enables aggressive voltage scaling which causes parametric (soft) failures in SRAM-based memory. As such, the proposed methodology can be utilized to exchange cache size for lower power or better yield. In the second methodology, data from faulty cells are treated as imposed noise. Depending on the application, this error percentage (imposed noise) can be mitigated through three options. First, ignore error if the percentage of the error is tolerable. Second, simple hardware filtration is needed. Finally, software-based filtration is required. The viability of this approach is that it allows aggressive voltage scaling below the traditional to be a 100% correct approach for SRAM supply, which results in substantial reduction of power, trading off quality for power. For both approaches, BIST is used as part of the powerup sequence to identify the faulty memory addresses per voltage level and compute the faulty cells percentage. Furthermore, the proposed methodologies help in improving reliability and counteracting long-term effects on memory cell stability and lifetime degradation caused by negative bias temperature instability.
@article{
 title = {Design Methodologies for Yield Enhancement and Power Efficiency in SRAM-Based SoCs},
 type = {article},
 year = {2015},
 identifiers = {[object Object]},
 keywords = {Caches,Voltage scaling,high yield,image processing,low power,memory architecture,static random-access memory (SRAM),system-on-a-chip (SoC) design},
 volume = {23},
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 abstract = {© 2015 IEEE. This paper comprises two new methodologies to improve yield and reduce system-on-a-chip power. The first methodology is based on faulty static random-access memory (SRAM) cells detections and cache resizing. The key advantage of this approach is that it enables the end user to control the system's parameters to be error tolerant. Furthermore, this technique enables aggressive voltage scaling which causes parametric (soft) failures in SRAM-based memory. As such, the proposed methodology can be utilized to exchange cache size for lower power or better yield. In the second methodology, data from faulty cells are treated as imposed noise. Depending on the application, this error percentage (imposed noise) can be mitigated through three options. First, ignore error if the percentage of the error is tolerable. Second, simple hardware filtration is needed. Finally, software-based filtration is required. The viability of this approach is that it allows aggressive voltage scaling below the traditional to be a 100% correct approach for SRAM supply, which results in substantial reduction of power, trading off quality for power. For both approaches, BIST is used as part of the powerup sequence to identify the faulty memory addresses per voltage level and compute the faulty cells percentage. Furthermore, the proposed methodologies help in improving reliability and counteracting long-term effects on memory cell stability and lifetime degradation caused by negative bias temperature instability.},
 bibtype = {article},
 author = {Mohammad, B.S. and Saleh, H. and Ismail, M.},
 journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
 number = {10}
}
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