Charge sharing aware NCL gates design. Moreira, M. T., Oliveira, B. S., Moraes, F. G., & Calazans, N. L. V. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, pages 212–217, 2013. IEEE Computer Society.
Charge sharing aware NCL gates design [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/dft/MoreiraOMC13,
  author       = {Matheus T. Moreira and
                  Bruno S. Oliveira and
                  Fernando Gehm Moraes and
                  Ney Laert Vilar Calazans},
  title        = {Charge sharing aware {NCL} gates design},
  booktitle    = {2013 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFTS} 2013, New York City,
                  NY, USA, October 2-4, 2013},
  pages        = {212--217},
  publisher    = {{IEEE} Computer Society},
  year         = {2013},
  url          = {https://doi.org/10.1109/DFT.2013.6653608},
  doi          = {10.1109/DFT.2013.6653608},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/MoreiraOMC13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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