An Optimized S-Box Circuit Architecture for Low Power AES Design. Morioka, S. & Satoh, A. In Kaliski, B. S., Koç, ç. K., & Paar, C., editors, Cryptographic Hardware and Embedded Systems - CHES 2002, of Lecture Notes in Computer Science, pages 172–186. Springer Berlin Heidelberg, August, 2002. ![An Optimized S-Box Circuit Architecture for Low Power AES Design [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi abstract bibtex Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems. We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, (i) the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and (ii) the hazard-transparent XOR gates are located after the other gates that may block the hazards. A low power consumption of 29 μW at 10 MHz using 0.13 μm 1.5V CMOS technology was achieved, while the consumptions of the BDD, SOP, and composite field S-Boxes are 275, 95, and 136 μW, respectively.
@incollection{morioka_optimized_2002,
series = {Lecture {Notes} in {Computer} {Science}},
title = {An {Optimized} {S}-{Box} {Circuit} {Architecture} for {Low} {Power} {AES} {Design}},
copyright = {©2003 Springer-Verlag Berlin Heidelberg},
isbn = {978-3-540-00409-7 978-3-540-36400-9},
url = {http://link.springer.com/chapter/10.1007/3-540-36400-5_14},
abstract = {Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems. We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, (i) the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and (ii) the hazard-transparent XOR gates are located after the other gates that may block the hazards. A low power consumption of 29 μW at 10 MHz using 0.13 μm 1.5V CMOS technology was achieved, while the consumptions of the BDD, SOP, and composite field S-Boxes are 275, 95, and 136 μW, respectively.},
language = {en},
number = {2523},
urldate = {2016-03-17TZ},
booktitle = {Cryptographic {Hardware} and {Embedded} {Systems} - {CHES} 2002},
publisher = {Springer Berlin Heidelberg},
author = {Morioka, Sumio and Satoh, Akashi},
editor = {Kaliski, Burton S. and Koç, çetin K. and Paar, Christof},
month = aug,
year = {2002},
doi = {10.1007/3-540-36400-5_14},
pages = {172--186}
}
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