Grouped through silicon vias for lower Ldi/dt drop in three-dimensional integrated circuit. Mossa, S. F., Hasan, S. R., & Elkeelany, O. S. A. IET Circuits, Devices & Systems, 10(1):44-53, 2016.
Grouped through silicon vias for lower Ldi/dt drop in three-dimensional integrated circuit. [link]Link  Grouped through silicon vias for lower Ldi/dt drop in three-dimensional integrated circuit. [link]Paper  bibtex   
@article{journals/iet-cds/MossaHE16,
  added-at = {2016-02-11T00:00:00.000+0100},
  author = {Mossa, Siraj Fulum and Hasan, Syed Rafay and Elkeelany, Omar Sayed Ahmed},
  biburl = {http://www.bibsonomy.org/bibtex/2bac787f9c0d482f42444540acf9306fc/dblp},
  ee = {http://dx.doi.org/10.1049/iet-cds.2015.0065},
  interhash = {9aa2b207b2c908aa01825f9aedae7983},
  intrahash = {bac787f9c0d482f42444540acf9306fc},
  journal = {IET Circuits, Devices & Systems},
  keywords = {dblp},
  number = 1,
  pages = {44-53},
  timestamp = {2016-02-12T11:36:43.000+0100},
  title = {Grouped through silicon vias for lower Ldi/dt drop in three-dimensional integrated circuit.},
  url = {http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds10.html#MossaHE16},
  volume = 10,
  year = 2016
}
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