5.6 A 0.13 #x03BC;m fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range. Nasir, S. B., Gangopadhyay, S., & Raychowdhury, A. In 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, pages 1–3, February, 2015. doi abstract bibtex This paper presents a discrete-time, fully digital, scan-programmable LDO macro in 0.13μm technology featuring greater than 90% current efficiency across a 50× current range, and 8× improvement in transient response time in response to large load steps. The baseline design features a 128b barrel shifter that digitally controls 128 identical power PMOS devices to provide load and line regulation at the node VREG, for a scan-programmable fine-grained synthetic load. A clocked comparator, which eliminates the need for any bias current, controls the direction of shift, D. The programmable mux-select signals, MUX1 and MUX2, provide controllable closed loop gains, KBARREL, of 1 to 3×. Since at any clock edge only 1, 2 or 3 shifts can occur (depending on the gain setting), fine-grained clock gating is enabled by dividing the 128b shifter into four sections and only enabling the clock to the section(s) where the shift occurs.
@inproceedings{nasir_5.6_2015,
title = {5.6 {A} 0.13 \#x03BC;m fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range},
doi = {10.1109/ISSCC.2015.7062944},
abstract = {This paper presents a discrete-time, fully digital, scan-programmable LDO macro in 0.13μm technology featuring greater than 90\% current efficiency across a 50× current range, and 8× improvement in transient response time in response to large load steps. The baseline design features a 128b barrel shifter that digitally controls 128 identical power PMOS devices to provide load and line regulation at the node VREG, for a scan-programmable fine-grained synthetic load. A clocked comparator, which eliminates the need for any bias current, controls the direction of shift, D. The programmable mux-select signals, MUX1 and MUX2, provide controllable closed loop gains, KBARREL, of 1 to 3×. Since at any clock edge only 1, 2 or 3 shifts can occur (depending on the gain setting), fine-grained clock gating is enabled by dividing the 128b shifter into four sections and only enabling the clock to the section(s) where the shift occurs.},
booktitle = {2015 {IEEE} {International} {Solid}-{State} {Circuits} {Conference} - ({ISSCC}) {Digest} of {Technical} {Papers}},
author = {Nasir, S. B. and Gangopadhyay, S. and Raychowdhury, A.},
month = feb,
year = {2015},
pages = {1--3}
}
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