Architectural Level Models for Subthreshold Leakage Power Estimation of SRAM Arrays with its Peripherals. Navlakha, N., Garg, L., Boolchandani, D., & Sahula, V. In 17th International Symposium on VLSI Design and Test, 2013, 2013. Paper bibtex @inproceedings{
title = {Architectural Level Models for Subthreshold Leakage Power Estimation of SRAM Arrays with its Peripherals},
type = {inproceedings},
year = {2013},
institution = {Springer, CICCS},
id = {1f9ff7a5-eaef-3955-afa3-382b29648a69},
created = {2014-04-17T21:17:22.000Z},
file_attached = {true},
profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
last_modified = {2017-03-14T01:22:09.162Z},
read = {false},
starred = {false},
authored = {true},
confirmed = {true},
hidden = {false},
citation_key = {NupurNavlakha2013},
source_type = {inproceedings},
private_publication = {false},
bibtype = {inproceedings},
author = {Navlakha, Nupur and Garg, Lokesh and Boolchandani, Dharmendar and Sahula, Vineet},
booktitle = {17th International Symposium on VLSI Design and Test, 2013}
}
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{"_id":"CktqvZy8BgBPSDDwB","bibbaseid":"navlakha-garg-boolchandani-sahula-architecturallevelmodelsforsubthresholdleakagepowerestimationofsramarrayswithitsperipherals-2013","author_short":["Navlakha, N.","Garg, L.","Boolchandani, D.","Sahula, V."],"bibdata":{"title":"Architectural Level Models for Subthreshold Leakage Power Estimation of SRAM Arrays with its Peripherals","type":"inproceedings","year":"2013","institution":"Springer, CICCS","id":"1f9ff7a5-eaef-3955-afa3-382b29648a69","created":"2014-04-17T21:17:22.000Z","file_attached":"true","profile_id":"03d2ca17-6bde-3cfe-95de-fcbe4f21507b","last_modified":"2017-03-14T01:22:09.162Z","read":false,"starred":false,"authored":"true","confirmed":"true","hidden":false,"citation_key":"NupurNavlakha2013","source_type":"inproceedings","private_publication":false,"bibtype":"inproceedings","author":"Navlakha, Nupur and Garg, Lokesh and Boolchandani, Dharmendar and Sahula, Vineet","booktitle":"17th International Symposium on VLSI Design and Test, 2013","bibtex":"@inproceedings{\n title = {Architectural Level Models for Subthreshold Leakage Power Estimation of SRAM Arrays with its Peripherals},\n type = {inproceedings},\n year = {2013},\n institution = {Springer, CICCS},\n id = {1f9ff7a5-eaef-3955-afa3-382b29648a69},\n created = {2014-04-17T21:17:22.000Z},\n file_attached = {true},\n profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},\n last_modified = {2017-03-14T01:22:09.162Z},\n read = {false},\n starred = {false},\n authored = {true},\n confirmed = {true},\n hidden = {false},\n citation_key = {NupurNavlakha2013},\n source_type = {inproceedings},\n private_publication = {false},\n bibtype = {inproceedings},\n author = {Navlakha, Nupur and Garg, Lokesh and Boolchandani, Dharmendar and Sahula, Vineet},\n booktitle = {17th International Symposium on VLSI Design and Test, 2013}\n}","author_short":["Navlakha, N.","Garg, L.","Boolchandani, D.","Sahula, V."],"urls":{"Paper":"https://bibbase.org/service/mendeley/03d2ca17-6bde-3cfe-95de-fcbe4f21507b/file/634689ed-a3d2-63d3-26b8-28c49e183ba1/2013-Architectural_Level_Models_for_Subthreshold_Leakage_Power_Estimation_of_SRAM_Arrays_with_its_Peripherals.pdf.pdf"},"biburl":"https://bibbase.org/service/mendeley/03d2ca17-6bde-3cfe-95de-fcbe4f21507b","bibbaseid":"navlakha-garg-boolchandani-sahula-architecturallevelmodelsforsubthresholdleakagepowerestimationofsramarrayswithitsperipherals-2013","role":"author","metadata":{"authorlinks":{}}},"bibtype":"inproceedings","biburl":"https://bibbase.org/service/mendeley/03d2ca17-6bde-3cfe-95de-fcbe4f21507b","dataSources":["YNoDN2TgaRvNK6vy3","ya2CyA73rpZseyrZ8"],"keywords":[],"search_terms":["architectural","level","models","subthreshold","leakage","power","estimation","sram","arrays","peripherals","navlakha","garg","boolchandani","sahula"],"title":"Architectural Level Models for Subthreshold Leakage Power Estimation of SRAM Arrays with its Peripherals","year":2013}