Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. Nelson, C. A., Myers, C. J., & Yoneda, T. IEEE Trans. on CAD of Integrated Circuits and Systems, 26(3):592–605, 2007. Paper doi bibtex @article{DBLP:journals/tcad/NelsonMY07,
author = {Curtis A. Nelson and
Chris J. Myers and
Tomohiro Yoneda},
title = {Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous
Circuits},
journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
volume = {26},
number = {3},
pages = {592--605},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.883912},
doi = {10.1109/TCAD.2006.883912},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/bib/journals/tcad/NelsonMY07},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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