In *The 45th Midwest Symposium on Circuits and Systems, (MWSCAS-2002)*, volume 1, pages I–647-50 vol.1, August, 2002.

abstract bibtex

abstract bibtex

This paper presents an efficient design and implementation of a low power sigma delta digital decimation filter. We implement a low power decimation filter with a narrow transition finite impulse response (FIR) filter using a canonic signed digit number (CSD) system. We use multi-stage multi-rate signal processing to design and implement half-band filters and narrow transition band FIR filters. The decimation filter is designed using Simulink, DSP Blockset and simulated using Matlab. The FIR filter has been coded in Verilog and implemented using FPGA Xilinx 4000 technology. The power consumption of the proposed decimation filter is reduced by 67% compared to the conventional 4-stage comb-FIR architecture.

@inproceedings{Nerurkar2002Low-power-, abstract = {This paper presents an efficient design and implementation of a low power sigma delta digital decimation filter. We implement a low power decimation filter with a narrow transition finite impulse response (FIR) filter using a canonic signed digit number (CSD) system. We use multi-stage multi-rate signal processing to design and implement half-band filters and narrow transition band FIR filters. The decimation filter is designed using Simulink, DSP Blockset and simulated using Matlab. The FIR filter has been coded in Verilog and implemented using FPGA Xilinx 4000 technology. The power consumption of the proposed decimation filter is reduced by 67{\%} compared to the conventional 4-stage comb-FIR architecture.}, author = {Nerurkar, Shailesh and Abed, Khalid and Siferd, Raymond and Venugopalan, Vivek}, booktitle = {The 45th Midwest Symposium on Circuits and Systems, (MWSCAS-2002)}, date-added = {2020-01-15 12:00:21 -0500}, date-modified = {2020-01-15 12:00:21 -0500}, keywords = {FIR filters; circuit simulation; comb filters; digital arithmetic; integrated circuit design; logic design; logic simulation; low-power electronics; sigma-delta modulation; CSD system; FPGA; canonic signed digit number system; comb filter; digital decimation filter; filter power consumption reduction; finite impulse response filter; half-band filters; low power filter; multi-rate signal processing; multi-stage signal processing; narrow transition FIR filter; sigma delta decimation filter; sigma delta modulator}, pages = {I--647-50 vol.1}, title = {Low Power Sigma Delta Decimation Filter}, ty = {CONF}, vo = {1}, volume = {1}, year = {2002}, month = aug, Bdsk-File-1 = {YnBsaXN0MDDSAQIDBFxyZWxhdGl2ZVBhdGhZYWxpYXNEYXRhXxAvLi4vLi4vcmVmZXJlbmNlcy9QREYvTmVydXJrYXIyMDAyTG93LXBvd2VyLS5wZGZPEQGMAAAAAAGMAAIAAAxNYWNpbnRvc2ggSEQAAAAAAAAAAAAAAAAAAAAAAAAAQkQAAf////8aTmVydXJrYXIyMDAyTG93LXBvd2VyLS5wZGYAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA/////wAAAAAAAAAAAAAAAAACAAMAAAogY3UAAAAAAAAAAAAAAAAAA1BERgAAAgBALzpVc2Vyczp2aXZla3Y6RHJvcGJveDpyZWZlcmVuY2VzOlBERjpOZXJ1cmthcjIwMDJMb3ctcG93ZXItLnBkZgAOADYAGgBOAGUAcgB1AHIAawBhAHIAMgAwADAAMgBMAG8AdwAtAHAAbwB3AGUAcgAtAC4AcABkAGYADwAaAAwATQBhAGMAaQBuAHQAbwBzAGgAIABIAEQAEgA+VXNlcnMvdml2ZWt2L0Ryb3Bib3gvcmVmZXJlbmNlcy9QREYvTmVydXJrYXIyMDAyTG93LXBvd2VyLS5wZGYAEwABLwAAFQACAA3//wAAAAgADQAaACQAVgAAAAAAAAIBAAAAAAAAAAUAAAAAAAAAAAAAAAAAAAHm}}

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