An index-free sparse neural network using two-dimensional semiconductor ferroelectric field-effect transistors. Ning, H., Wen, H., Meng, Y., Yu, Z., Fu, Y., Zou, X., Shen, Y., Luo, X., Zhao, Q., Zhang, T., Liu, L., Zhu, S., Li, T., Li, W., Li, L., Gao, L., Shi, Y., & Wang, X. Nature Electronics, January, 2025. Publisher: Nature Publishing Group![An index-free sparse neural network using two-dimensional semiconductor ferroelectric field-effect transistors [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi abstract bibtex The fine-grained dynamic sparsity in biological synapses is an important element in the energy efficiency of the human brain. Emulating such sparsity in an artificial system requires off-chip memory indexing, which has a considerable energy and latency overhead. Here, we report an in-memory sparsity architecture in which index memory is moved next to individual synapses, creating a sparse neural network without external memory indexing. We use a compact building block consisting of two non-volatile ferroelectric field-effect transistors acting as a digital sparsity and an analogue weight. The network is formulated as the Hadamard product of the sparsity and weight matrices, and the hardware, which is comprised of 900 ferroelectric field-effect transistors, is based on wafer-scale chemical-vapour-deposited molybdenum disulfide integrated through back-end-of-line processes. With the system, we demonstrate key synaptic processes—including pruning, weight update and regrowth—in an unstructured and fine-grained manner. We also develop a vectorial approximate update algorithm and optimize training scheduling. Through this software–hardware co-optimization, we achieve 98.4% accuracy in an EMNIST letter recognition task under 75% sparsity. Simulations on large neural networks show a tenfold reduction in latency and a ninefold reduction in energy consumption when compared with a dense network of the same performance.
@article{ning_index-free_2025,
title = {An index-free sparse neural network using two-dimensional semiconductor ferroelectric field-effect transistors},
copyright = {2025 The Author(s), under exclusive licence to Springer Nature Limited},
issn = {2520-1131},
url = {https://www.nature.com/articles/s41928-024-01328-4},
doi = {10.1038/s41928-024-01328-4},
abstract = {The fine-grained dynamic sparsity in biological synapses is an important element in the energy efficiency of the human brain. Emulating such sparsity in an artificial system requires off-chip memory indexing, which has a considerable energy and latency overhead. Here, we report an in-memory sparsity architecture in which index memory is moved next to individual synapses, creating a sparse neural network without external memory indexing. We use a compact building block consisting of two non-volatile ferroelectric field-effect transistors acting as a digital sparsity and an analogue weight. The network is formulated as the Hadamard product of the sparsity and weight matrices, and the hardware, which is comprised of 900 ferroelectric field-effect transistors, is based on wafer-scale chemical-vapour-deposited molybdenum disulfide integrated through back-end-of-line processes. With the system, we demonstrate key synaptic processes—including pruning, weight update and regrowth—in an unstructured and fine-grained manner. We also develop a vectorial approximate update algorithm and optimize training scheduling. Through this software–hardware co-optimization, we achieve 98.4\% accuracy in an EMNIST letter recognition task under 75\% sparsity. Simulations on large neural networks show a tenfold reduction in latency and a ninefold reduction in energy consumption when compared with a dense network of the same performance.},
language = {en},
urldate = {2025-01-10},
journal = {Nature Electronics},
author = {Ning, Hongkai and Wen, Hengdi and Meng, Yuan and Yu, Zhihao and Fu, Yuxiang and Zou, Xilu and Shen, Yilin and Luo, Xiai and Zhao, Qiyue and Zhang, Tao and Liu, Lei and Zhu, Shitong and Li, Taotao and Li, Weisheng and Li, Li and Gao, Li and Shi, Yi and Wang, Xinran},
month = jan,
year = {2025},
note = {Publisher: Nature Publishing Group},
keywords = {Electronic devices, Two-dimensional materials},
pages = {1--13},
}
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Emulating such sparsity in an artificial system requires off-chip memory indexing, which has a considerable energy and latency overhead. Here, we report an in-memory sparsity architecture in which index memory is moved next to individual synapses, creating a sparse neural network without external memory indexing. We use a compact building block consisting of two non-volatile ferroelectric field-effect transistors acting as a digital sparsity and an analogue weight. The network is formulated as the Hadamard product of the sparsity and weight matrices, and the hardware, which is comprised of 900 ferroelectric field-effect transistors, is based on wafer-scale chemical-vapour-deposited molybdenum disulfide integrated through back-end-of-line processes. With the system, we demonstrate key synaptic processes—including pruning, weight update and regrowth—in an unstructured and fine-grained manner. We also develop a vectorial approximate update algorithm and optimize training scheduling. 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Emulating such sparsity in an artificial system requires off-chip memory indexing, which has a considerable energy and latency overhead. Here, we report an in-memory sparsity architecture in which index memory is moved next to individual synapses, creating a sparse neural network without external memory indexing. We use a compact building block consisting of two non-volatile ferroelectric field-effect transistors acting as a digital sparsity and an analogue weight. The network is formulated as the Hadamard product of the sparsity and weight matrices, and the hardware, which is comprised of 900 ferroelectric field-effect transistors, is based on wafer-scale chemical-vapour-deposited molybdenum disulfide integrated through back-end-of-line processes. With the system, we demonstrate key synaptic processes—including pruning, weight update and regrowth—in an unstructured and fine-grained manner. We also develop a vectorial approximate update algorithm and optimize training scheduling. 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