A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. Oh, T., Chung, H., Park, J., Lee, K., Oh, S., Doo, S., Kim, H., Lee, C., Kim, H., Lee, J., Lee, J., Ha, K., Choi, Y., Cho, Y., Bae, Y., Jang, T., Park, C., Park, K., Jang, S., & Choi, J. J. Solid-State Circuits (JSSC), 50(1):178-190, 2015. ![A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper bibtex @article{ dblp1865765,
title = {A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation},
author = {Tae-Young Oh and Hoeju Chung and Jun-Young Park and Ki-Won Lee and Seunghoon Oh and Su-Yeon Doo and Hyoung-Joo Kim and ChangYong Lee and Hye-Ran Kim and Jong-Ho Lee and Jin-Il Lee and Kyung-Soo Ha and Young-Ryeol Choi and Young-Chul Cho and Yong-Cheol Bae and Taeseong Jang and Chulsung Park and Kwang-Il Park and Seong-Jin Jang and Joo-Sun Choi},
author_short = {Oh, T. and Chung, H. and Park, J. and Lee, K. and Oh, S. and Doo, S. and Kim, H. and Lee, C. and Kim, H. and Lee, J. and Lee, J. and Ha, K. and Choi, Y. and Cho, Y. and Bae, Y. and Jang, T. and Park, C. and Park, K. and Jang, S. and Choi, J.},
bibtype = {article},
type = {article},
year = {2015},
key = {dblp1865765},
id = {dblp1865765},
biburl = {http://www.dblp.org/rec/bibtex/journals/jssc/OhCPLODKLKLLHCCBJPPJC15},
url = {http://dx.doi.org/10.1109/JSSC.2014.2353799},
journal = {J. Solid-State Circuits (JSSC)},
pages = {178-190},
number = {1},
volume = {50},
text = {J. Solid-State Circuits (JSSC) 50(1):178-190 (2015)}
}
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