A simplified executable model to evaluate latency and throughput of networks-on-chip. Ost, L., Moraes, F. G., Möller, L., Indrusiak, L. S., Glesner, M., Määttä, S., & Nurmi, J. In Lubaszewski, M., Renovell, M., & Gupta, R. K., editors, Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pages 170–175, 2008. ACM.
Paper doi bibtex @inproceedings{DBLP:conf/sbcci/OstMMIGMN08,
author = {Luciano Ost and
Fernando Gehm Moraes and
Leandro M{\"{o}}ller and
Leandro Soares Indrusiak and
Manfred Glesner and
Sanna M{\"{a}}{\"{a}}tt{\"{a}} and
Jari Nurmi},
editor = {Marcelo Lubaszewski and
Michel Renovell and
Rajesh K. Gupta},
title = {A simplified executable model to evaluate latency and throughput of
networks-on-chip},
booktitle = {Proceedings of the 21st Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2008, Gramado, Brazil, September 1-4, 2008},
pages = {170--175},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1404371.1404420},
doi = {10.1145/1404371.1404420},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/OstMMIGMN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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{"_id":"3oXvFQxu2xTaDbkmh","bibbaseid":"ost-moraes-mller-indrusiak-glesner-mtt-nurmi-asimplifiedexecutablemodeltoevaluatelatencyandthroughputofnetworksonchip-2008","downloads":0,"creationDate":"2018-05-18T14:18:41.400Z","title":"A simplified executable model to evaluate latency and throughput of networks-on-chip","author_short":["Ost, L.","Moraes, F. G.","Möller, L.","Indrusiak, L. S.","Glesner, M.","Määttä, S.","Nurmi, J."],"year":2008,"bibtype":"inproceedings","biburl":"https://dblp.org/pid/m/FernandoGehmMoraes.bib","bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"firstnames":["Luciano"],"propositions":[],"lastnames":["Ost"],"suffixes":[]},{"firstnames":["Fernando","Gehm"],"propositions":[],"lastnames":["Moraes"],"suffixes":[]},{"firstnames":["Leandro"],"propositions":[],"lastnames":["Möller"],"suffixes":[]},{"firstnames":["Leandro","Soares"],"propositions":[],"lastnames":["Indrusiak"],"suffixes":[]},{"firstnames":["Manfred"],"propositions":[],"lastnames":["Glesner"],"suffixes":[]},{"firstnames":["Sanna"],"propositions":[],"lastnames":["Määttä"],"suffixes":[]},{"firstnames":["Jari"],"propositions":[],"lastnames":["Nurmi"],"suffixes":[]}],"editor":[{"firstnames":["Marcelo"],"propositions":[],"lastnames":["Lubaszewski"],"suffixes":[]},{"firstnames":["Michel"],"propositions":[],"lastnames":["Renovell"],"suffixes":[]},{"firstnames":["Rajesh","K."],"propositions":[],"lastnames":["Gupta"],"suffixes":[]}],"title":"A simplified executable model to evaluate latency and throughput of networks-on-chip","booktitle":"Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008","pages":"170–175","publisher":"ACM","year":"2008","url":"https://doi.org/10.1145/1404371.1404420","doi":"10.1145/1404371.1404420","timestamp":"Sun, 02 Oct 2022 01:00:00 +0200","biburl":"https://dblp.org/rec/conf/sbcci/OstMMIGMN08.bib","bibsource":"dblp computer science bibliography, https://dblp.org","bibtex":"@inproceedings{DBLP:conf/sbcci/OstMMIGMN08,\n author = {Luciano Ost and\n Fernando Gehm Moraes and\n Leandro M{\\\"{o}}ller and\n Leandro Soares Indrusiak and\n Manfred Glesner and\n Sanna M{\\\"{a}}{\\\"{a}}tt{\\\"{a}} and\n Jari Nurmi},\n editor = {Marcelo Lubaszewski and\n Michel Renovell and\n Rajesh K. Gupta},\n title = {A simplified executable model to evaluate latency and throughput of\n networks-on-chip},\n booktitle = {Proceedings of the 21st Annual Symposium on Integrated Circuits and\n Systems Design, {SBCCI} 2008, Gramado, Brazil, September 1-4, 2008},\n pages = {170--175},\n publisher = {{ACM}},\n year = {2008},\n url = {https://doi.org/10.1145/1404371.1404420},\n doi = {10.1145/1404371.1404420},\n timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},\n biburl = {https://dblp.org/rec/conf/sbcci/OstMMIGMN08.bib},\n bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n","author_short":["Ost, L.","Moraes, F. G.","Möller, L.","Indrusiak, L. S.","Glesner, M.","Määttä, S.","Nurmi, J."],"editor_short":["Lubaszewski, M.","Renovell, M.","Gupta, R. K."],"key":"DBLP:conf/sbcci/OstMMIGMN08","id":"DBLP:conf/sbcci/OstMMIGMN08","bibbaseid":"ost-moraes-mller-indrusiak-glesner-mtt-nurmi-asimplifiedexecutablemodeltoevaluatelatencyandthroughputofnetworksonchip-2008","role":"author","urls":{"Paper":"https://doi.org/10.1145/1404371.1404420"},"metadata":{"authorlinks":{"moraes, f":"https://www.inf.pucrs.br/"}}},"search_terms":["simplified","executable","model","evaluate","latency","throughput","networks","chip","ost","moraes","möller","indrusiak","glesner","määttä","nurmi"],"keywords":[],"authorIDs":["aZmE7qmCtnswuExac"],"dataSources":["pEib8arMvtjpTWFyZ"]}