A simplified executable model to evaluate latency and throughput of networks-on-chip. Ost, L., Moraes, F. G., Möller, L., Indrusiak, L. S., Glesner, M., Määttä, S., & Nurmi, J. In Lubaszewski, M., Renovell, M., & Gupta, R. K., editors, Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pages 170–175, 2008. ACM.
A simplified executable model to evaluate latency and throughput of networks-on-chip [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/sbcci/OstMMIGMN08,
  author    = {Luciano Ost and
               Fernando Gehm Moraes and
               Leandro M{\"{o}}ller and
               Leandro Soares Indrusiak and
               Manfred Glesner and
               Sanna M{\"{a}}{\"{a}}tt{\"{a}} and
               Jari Nurmi},
  editor    = {Marcelo Lubaszewski and
               Michel Renovell and
               Rajesh K. Gupta},
  title     = {A simplified executable model to evaluate latency and throughput of
               networks-on-chip},
  booktitle = {Proceedings of the 21st Annual Symposium on Integrated Circuits and
               Systems Design, {SBCCI} 2008, Gramado, Brazil, September 1-4, 2008},
  pages     = {170--175},
  publisher = {{ACM}},
  year      = {2008},
  url       = {https://doi.org/10.1145/1404371.1404420},
  doi       = {10.1145/1404371.1404420},
  timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/sbcci/OstMMIGMN08.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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