Hierarchical Modeling and Verification of Timed Systems in Timed AltaRica. Pagetti, C., Cassez, F., & Roux, O. In Formal Aspects of Component Software (FACS'03), pages 63–80, September, 2003. UNU/IIST, Macau. Pisa, Italy, September 8–9, 2003
Hierarchical Modeling and Verification of Timed Systems in Timed AltaRica [pdf]Paper  Hierarchical Modeling and Verification of Timed Systems in Timed AltaRica [link]Link  abstract   bibtex   
In this paper we present a timed extension of the AltaRica language, Timed AltaRica, and describe the architecture of a compiler from Timed AltaRica to timed automata. We present the features of the language, namely modularity, hierarchical modeling and reuse of components during the specification phase, on an avionics example. Then, we use the compiler from Timed AltaRica to Timed Automata to check some safety properties on the system.

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