@inproceedings{conf/ised/PalVPVM14,
  added-at = {2020-06-15T00:00:00.000+0200},
  author = {Pal, Subhankar and Vudadha, Chetan and P., Sai Phaneendra and Veeramachaneni, Sreehari and Mandalika, Srinivas B.},
  biburl = {https://www.bibsonomy.org/bibtex/2bee9df83e41cb1653bc5e5003a7e29a9/dblp},
  booktitle = {ISED},
  crossref = {conf/ised/2014},
  ee = {https://doi.org/10.1109/ISED.2014.56},
  interhash = {0c5f88ddcbca9c61955305a16404e6da},
  intrahash = {bee9df83e41cb1653bc5e5003a7e29a9},
  isbn = {978-1-4799-6965-4},
  keywords = {dblp},
  pages = {224-225},
  publisher = {IEEE Computer Society},
  timestamp = {2020-06-16T12:12:32.000+0200},
  title = {A New Design of an N-Bit Reversible Arithmetic Logic Unit.},
  url = {http://dblp.uni-trier.de/db/conf/ised/ised2014.html#PalVPVM14},
  year = 2014
}

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