On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures. Parcerisa, J., Sahuquillo, J., González, A., & Duato, J. IEEE Trans. Parallel Distrib. Syst., 16(2):130-144, 2005. Link Paper bibtex @article{journals/tpds/ParcerisaSG05,
added-at = {2016-01-16T00:00:00.000+0100},
author = {Parcerisa, Joan-Manuel and Sahuquillo, Julio and González, Antonio and Duato, José},
biburl = {http://www.bibsonomy.org/bibtex/2aabbef0ee939faf21ad3bcbf55adcbd7/dblp},
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journal = {IEEE Trans. Parallel Distrib. Syst.},
keywords = {dblp},
number = 2,
pages = {130-144},
timestamp = {2016-01-19T11:37:45.000+0100},
title = {On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures.},
url = {http://dblp.uni-trier.de/db/journals/tpds/tpds16.html#ParcerisaSG05},
volume = 16,
year = 2005
}
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