A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic. Patel, H., Roy, A., Yahya, F. B., Liu, N., Calhoun, B. H., Harada, A., Kumeno, K., Yasuda, M., & Ema, T. IEICE Technical Report; IEICE Tech. Rep., 2017.
A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic [link]Paper  bibtex   
@article{664,
  author = {Harsh Patel and Abhishek Roy and Farah B. Yahya and Ningxi Liu and Benton H. Calhoun and Ayako Harada and Kazuyuki Kumeno and Makoto Yasuda and T. Ema},
  title = {A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic},
  year = {2017},
  journal = {IEICE Technical Report; IEICE Tech. Rep.},
  url = {https://www.ieice.org/ken/paper/20170421pbsr/eng/}
}

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