@inproceedings{
 title = {Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration},
 type = {inproceedings},
 year = {2012},
 keywords = {Arrays,Cohn Kanade database,Dynamic partial reconfiguration,FPGA,Field programmable gate arrays,Hardware,SVM,Support vector machines,Systolic array,Training,Vectors,XILINX EDA tools,anger,complexity reduction,data transfer mechanisms,disgust,dynamic partial reconfiguration,emotion recognition,face recognition,facial expression recognition system,fear,field programmable gate arrays,image classification,memory management,multiclass SVM classifier,pair wise classifier classification,parameter extraction,partial reconfiguration schemes,power aware computing,power aware hardware prototyping,sad,smile,support vector machines,surprise,systolic array,systolic array architecture,systolic arrays,vector multiplication operation,vectors},
 pages = {62-67},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6167729},
 month = {1},
 publisher = {IEEE},
 id = {218427d5-8a93-3fdc-bc49-d57deea469e3},
 created = {2016-04-21T16:39:31.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Patil2012},
 short_title = {VLSI Design (VLSID), 2012 25th International Confe},
 private_publication = {false},
 abstract = {This paper presents power aware hardware implementation of multiclass Support Vector Machine on FPGA using systolic array architecture. It uses Partial reconfiguration schemes of XILINX for power optimal implementation of the design. Systolic array architecture provides efficient memory management, reduced complexity, and efficient data transfer mechanisms. Multiclass support vector machine is used as classifier for facial expression recognition system, which identifies one of six basic facial expressions such as smile, surprise, sad, anger, disgust, and fear. The extracted parameters from training phase of the SVM are used to implement testing phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pair wise classifiers is designed. A data set of Cohn Kanade database in six different classes is used for training and testing of proposed SVM. This architecture is then partially reconfigured using difference based approach with the help of XILINX EDA tools. For feature classification power reduction is achieved using reconfiguration.},
 bibtype = {inproceedings},
 author = {Patil, Rajesh A. and Gupta, Gauri and Sahula, Vineet and Mandal, A.S. S.},
 doi = {10.1109/VLSID.2012.47},
 booktitle = {Proceedings of the IEEE International Conference on VLSI Design}
}

{"_id":"WKq4CQPgbeGZiXZxb","bibbaseid":"patil-gupta-sahula-mandal-powerawarehardwareprototypingofmulticlasssvmclassifierthroughreconfiguration-2012","author_short":["Patil, R., A.","Gupta, G.","Sahula, V.","Mandal, A., S."],"bibdata":{"title":"Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration","type":"inproceedings","year":"2012","keywords":"Arrays,Cohn Kanade database,Dynamic partial reconfiguration,FPGA,Field programmable gate arrays,Hardware,SVM,Support vector machines,Systolic array,Training,Vectors,XILINX EDA tools,anger,complexity reduction,data transfer mechanisms,disgust,dynamic partial reconfiguration,emotion recognition,face recognition,facial expression recognition system,fear,field programmable gate arrays,image classification,memory management,multiclass SVM classifier,pair wise classifier classification,parameter extraction,partial reconfiguration schemes,power aware computing,power aware hardware prototyping,sad,smile,support vector machines,surprise,systolic array,systolic array architecture,systolic arrays,vector multiplication operation,vectors","pages":"62-67","websites":"http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6167729","month":"1","publisher":"IEEE","id":"218427d5-8a93-3fdc-bc49-d57deea469e3","created":"2016-04-21T16:39:31.000Z","accessed":"2015-12-15","file_attached":"true","profile_id":"03d2ca17-6bde-3cfe-95de-fcbe4f21507b","last_modified":"2017-03-14T01:22:09.162Z","read":false,"starred":false,"authored":"true","confirmed":"true","hidden":false,"citation_key":"Patil2012","short_title":"VLSI Design (VLSID), 2012 25th International Confe","private_publication":false,"abstract":"This paper presents power aware hardware implementation of multiclass Support Vector Machine on FPGA using systolic array architecture. It uses Partial reconfiguration schemes of XILINX for power optimal implementation of the design. Systolic array architecture provides efficient memory management, reduced complexity, and efficient data transfer mechanisms. Multiclass support vector machine is used as classifier for facial expression recognition system, which identifies one of six basic facial expressions such as smile, surprise, sad, anger, disgust, and fear. The extracted parameters from training phase of the SVM are used to implement testing phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pair wise classifiers is designed. A data set of Cohn Kanade database in six different classes is used for training and testing of proposed SVM. This architecture is then partially reconfigured using difference based approach with the help of XILINX EDA tools. For feature classification power reduction is achieved using reconfiguration.","bibtype":"inproceedings","author":"Patil, Rajesh A. and Gupta, Gauri and Sahula, Vineet and Mandal, A.S. S.","doi":"10.1109/VLSID.2012.47","booktitle":"Proceedings of the IEEE International Conference on VLSI Design","bibtex":"@inproceedings{\n title = {Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration},\n type = {inproceedings},\n year = {2012},\n keywords = {Arrays,Cohn Kanade database,Dynamic partial reconfiguration,FPGA,Field programmable gate arrays,Hardware,SVM,Support vector machines,Systolic array,Training,Vectors,XILINX EDA tools,anger,complexity reduction,data transfer mechanisms,disgust,dynamic partial reconfiguration,emotion recognition,face recognition,facial expression recognition system,fear,field programmable gate arrays,image classification,memory management,multiclass SVM classifier,pair wise classifier classification,parameter extraction,partial reconfiguration schemes,power aware computing,power aware hardware prototyping,sad,smile,support vector machines,surprise,systolic array,systolic array architecture,systolic arrays,vector multiplication operation,vectors},\n pages = {62-67},\n websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6167729},\n month = {1},\n publisher = {IEEE},\n id = {218427d5-8a93-3fdc-bc49-d57deea469e3},\n created = {2016-04-21T16:39:31.000Z},\n accessed = {2015-12-15},\n file_attached = {true},\n profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},\n last_modified = {2017-03-14T01:22:09.162Z},\n read = {false},\n starred = {false},\n authored = {true},\n confirmed = {true},\n hidden = {false},\n citation_key = {Patil2012},\n short_title = {VLSI Design (VLSID), 2012 25th International Confe},\n private_publication = {false},\n abstract = {This paper presents power aware hardware implementation of multiclass Support Vector Machine on FPGA using systolic array architecture. It uses Partial reconfiguration schemes of XILINX for power optimal implementation of the design. Systolic array architecture provides efficient memory management, reduced complexity, and efficient data transfer mechanisms. Multiclass support vector machine is used as classifier for facial expression recognition system, which identifies one of six basic facial expressions such as smile, surprise, sad, anger, disgust, and fear. The extracted parameters from training phase of the SVM are used to implement testing phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pair wise classifiers is designed. A data set of Cohn Kanade database in six different classes is used for training and testing of proposed SVM. This architecture is then partially reconfigured using difference based approach with the help of XILINX EDA tools. For feature classification power reduction is achieved using reconfiguration.},\n bibtype = {inproceedings},\n author = {Patil, Rajesh A. and Gupta, Gauri and Sahula, Vineet and Mandal, A.S. S.},\n doi = {10.1109/VLSID.2012.47},\n booktitle = {Proceedings of the IEEE International Conference on VLSI Design}\n}","author_short":["Patil, R., A.","Gupta, G.","Sahula, V.","Mandal, A., S."],"urls":{"Paper":"https://bibbase.org/service/mendeley/03d2ca17-6bde-3cfe-95de-fcbe4f21507b/file/34dbad5c-d38b-4dab-3077-1b2000113fad/2012-Power_Aware_Hardware_Prototyping_of_Multiclass_SVM_Classifier_Through_Reconfiguration.pdf.pdf","Website":"http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6167729"},"biburl":"https://bibbase.org/service/mendeley/03d2ca17-6bde-3cfe-95de-fcbe4f21507b","bibbaseid":"patil-gupta-sahula-mandal-powerawarehardwareprototypingofmulticlasssvmclassifierthroughreconfiguration-2012","role":"author","keyword":["Arrays","Cohn Kanade database","Dynamic partial reconfiguration","FPGA","Field programmable gate arrays","Hardware","SVM","Support vector machines","Systolic array","Training","Vectors","XILINX EDA tools","anger","complexity reduction","data transfer mechanisms","disgust","dynamic partial reconfiguration","emotion recognition","face recognition","facial expression recognition system","fear","field programmable gate arrays","image classification","memory management","multiclass SVM classifier","pair wise classifier classification","parameter extraction","partial reconfiguration schemes","power aware computing","power aware hardware prototyping","sad","smile","support vector machines","surprise","systolic array","systolic array architecture","systolic arrays","vector multiplication operation","vectors"],"metadata":{"authorlinks":{}}},"bibtype":"inproceedings","biburl":"https://bibbase.org/service/mendeley/03d2ca17-6bde-3cfe-95de-fcbe4f21507b","dataSources":["foRZzjCMmTPmTF8eH","ya2CyA73rpZseyrZ8"],"keywords":["arrays","cohn kanade database","dynamic partial reconfiguration","fpga","field programmable gate arrays","hardware","svm","support vector machines","systolic array","training","vectors","xilinx eda tools","anger","complexity reduction","data transfer mechanisms","disgust","dynamic partial reconfiguration","emotion recognition","face recognition","facial expression recognition system","fear","field programmable gate arrays","image classification","memory management","multiclass svm classifier","pair wise classifier classification","parameter extraction","partial reconfiguration schemes","power aware computing","power aware hardware prototyping","sad","smile","support vector machines","surprise","systolic array","systolic array architecture","systolic arrays","vector multiplication operation","vectors"],"search_terms":["power","aware","hardware","prototyping","multiclass","svm","classifier","through","reconfiguration","patil","gupta","sahula","mandal"],"title":"Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration","year":2012}