Rapid embedded hardware/software system generation. Peddersen, J., Shee, Lin, S., Janapsatya, A., & Parameswaran, S. In 18th International Conference on VLSI Design (VLSI Design '05), pages 111-16, Kolkata, India, 2005. IEEE Computer Soc. 8349108 embedded hardware system generation embedded software system generation RTL generation scheme SimpleScalar/PISA instruction set system calls C programs ASIPmeister processor generation tool PISA instruction set processor size energy consumption processor performanceabstract bibtex This paper presents an RTL generation scheme for a SimpleScalar/PISA instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a processor generation tool. The RTL generated is available for download. The second part of the paper shows a method of reducing the PISA instruction set and generating a processor for a given application. This reduction and generation can be performed within an hour, making this one of the fastest methods of generating an application specific processor. For five benchmark applications, we show that on average, processor size can be reduced by 30%, energy consumed reduced by 24%, and performance improved by 24%
@inproceedings{ Jorgen05,
author = {Peddersen, Jorgen and Shee, Seng Lin and Andhi Janapsatya and Parameswaran,
Sri},
title = {Rapid embedded hardware/software system generation},
booktitle = {18th International Conference on VLSI Design (VLSI Design '05)},
year = {2005},
pages = {111-16},
address = {Kolkata, India},
publisher = {IEEE Computer Soc},
note = {8349108 embedded hardware system generation embedded software system
generation RTL generation scheme SimpleScalar/PISA instruction set
system calls C programs ASIPmeister processor generation tool PISA
instruction set processor size energy consumption processor performance},
abstract = {This paper presents an RTL generation scheme for a SimpleScalar/PISA
instruction set architecture with system calls to implement C programs.
The scheme utilizes ASIPmeister, a processor generation tool. The
RTL generated is available for download. The second part of the paper
shows a method of reducing the PISA instruction set and generating
a processor for a given application. This reduction and generation
can be performed within an hour, making this one of the fastest methods
of generating an application specific processor. For five benchmark
applications, we show that on average, processor size can be reduced
by 30%, energy consumed reduced by 24%, and performance improved
by 24%},
keywords = {application specific integrated circuits C language embedded systems
microprocessor chips},
pdf = {http://www.cse.unsw.edu.au/~sridevan/index_files/01383262.pdf}
}
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