@inproceedings{ Jorgen05,
  author = {Peddersen, Jorgen and Shee, Seng Lin and Andhi Janapsatya and Parameswaran,
	Sri},
  title = {Rapid embedded hardware/software system generation},
  booktitle = {18th International Conference on VLSI Design (VLSI Design '05)},
  year = {2005},
  pages = {111-16},
  address = {Kolkata, India},
  publisher = {IEEE Computer Soc},
  note = {8349108 embedded hardware system generation embedded software system
	generation RTL generation scheme SimpleScalar/PISA instruction set
	system calls C programs ASIPmeister processor generation tool PISA
	instruction set processor size energy consumption processor performance},
  abstract = {This paper presents an RTL generation scheme for a SimpleScalar/PISA
	instruction set architecture with system calls to implement C programs.
	The scheme utilizes ASIPmeister, a processor generation tool. The
	RTL generated is available for download. The second part of the paper
	shows a method of reducing the PISA instruction set and generating
	a processor for a given application. This reduction and generation
	can be performed within an hour, making this one of the fastest methods
	of generating an application specific processor. For five benchmark
	applications, we show that on average, processor size can be reduced
	by 30%, energy consumed reduced by 24%, and performance improved
	by 24%},
  keywords = {application specific integrated circuits C language embedded systems
	microprocessor chips},
  pdf = {http://www.cse.unsw.edu.au/~sridevan/index_files/01383262.pdf}
}

{"_id":"9HHiepEzte8gC8S2E","authorIDs":[],"author_short":["Peddersen, J.","Shee","Lin, S.","Janapsatya, A.","Parameswaran, S."],"bibbaseid":"peddersen-shee-lin-janapsatya-parameswaran-rapidembeddedhardwaresoftwaresystemgeneration-2005","bibdata":{"abstract":"This paper presents an RTL generation scheme for a SimpleScalar/PISA instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a processor generation tool. The RTL generated is available for download. The second part of the paper shows a method of reducing the PISA instruction set and generating a processor for a given application. This reduction and generation can be performed within an hour, making this one of the fastest methods of generating an application specific processor. For five benchmark applications, we show that on average, processor size can be reduced by 30%, energy consumed reduced by 24%, and performance improved by 24%","address":"Kolkata, India","author":["Peddersen, Jorgen","Shee","Lin, Seng","Janapsatya, Andhi","Parameswaran, Sri"],"author_short":["Peddersen, J.","Shee","Lin, S.","Janapsatya, A.","Parameswaran, S."],"bibtex":"@inproceedings{ Jorgen05,\n author = {Peddersen, Jorgen and Shee, Seng Lin and Andhi Janapsatya and Parameswaran,\r\n\tSri},\n title = {Rapid embedded hardware/software system generation},\n booktitle = {18th International Conference on VLSI Design (VLSI Design '05)},\n year = {2005},\n pages = {111-16},\n address = {Kolkata, India},\n publisher = {IEEE Computer Soc},\n note = {8349108 embedded hardware system generation embedded software system\r\n\tgeneration RTL generation scheme SimpleScalar/PISA instruction set\r\n\tsystem calls C programs ASIPmeister processor generation tool PISA\r\n\tinstruction set processor size energy consumption processor performance},\n abstract = {This paper presents an RTL generation scheme for a SimpleScalar/PISA\r\n\tinstruction set architecture with system calls to implement C programs.\r\n\tThe scheme utilizes ASIPmeister, a processor generation tool. The\r\n\tRTL generated is available for download. The second part of the paper\r\n\tshows a method of reducing the PISA instruction set and generating\r\n\ta processor for a given application. This reduction and generation\r\n\tcan be performed within an hour, making this one of the fastest methods\r\n\tof generating an application specific processor. For five benchmark\r\n\tapplications, we show that on average, processor size can be reduced\r\n\tby 30%, energy consumed reduced by 24%, and performance improved\r\n\tby 24%},\n keywords = {application specific integrated circuits C language embedded systems\r\n\tmicroprocessor chips},\n pdf = {http://www.cse.unsw.edu.au/~sridevan/index_files/01383262.pdf}\n}","bibtype":"inproceedings","booktitle":"18th International Conference on VLSI Design (VLSI Design '05)","id":"Jorgen05","key":"Jorgen05","keywords":"application specific integrated circuits C language embedded systems microprocessor chips","note":"8349108 embedded hardware system generation embedded software system generation RTL generation scheme SimpleScalar/PISA instruction set system calls C programs ASIPmeister processor generation tool PISA instruction set processor size energy consumption processor performance","pages":"111-16","pdf":"http://www.cse.unsw.edu.au/~sridevan/index_files/01383262.pdf","publisher":"IEEE Computer Soc","title":"Rapid embedded hardware/software system generation","type":"inproceedings","year":"2005","bibbaseid":"peddersen-shee-lin-janapsatya-parameswaran-rapidembeddedhardwaresoftwaresystemgeneration-2005","role":"author","urls":{},"keyword":["application specific integrated circuits C language embedded systems microprocessor chips"],"downloads":0,"html":""},"bibtype":"inproceedings","biburl":"http://www.cse.unsw.edu.au/~sridevan/pubs/Document.bib","creationDate":"2014-12-11T20:17:25.683Z","downloads":0,"keywords":["application specific integrated circuits c language embedded systems microprocessor chips"],"search_terms":["rapid","embedded","hardware","software","system","generation","peddersen","shee","lin","janapsatya","parameswaran"],"title":"Rapid embedded hardware/software system generation","year":2005,"dataSources":["qmNv3eFxXczLaRktj"]}