Securing Hardware Accelerators: A New Challenge for High-Level Synthesis. Pilato, C., Garg, S., Wu, K., Karri, R., & Regazzoni, F. IEEE Embed. Syst. Lett., 10(3):77–80, 2018. Paper doi bibtex @article{DBLP:journals/esl/PilatoGWKR18,
author = {Christian Pilato and
Siddharth Garg and
Kaijie Wu and
Ramesh Karri and
Francesco Regazzoni},
title = {Securing Hardware Accelerators: {A} New Challenge for High-Level Synthesis},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {10},
number = {3},
pages = {77--80},
year = {2018},
url = {https://doi.org/10.1109/LES.2017.2774800},
doi = {10.1109/LES.2017.2774800},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/PilatoGWKR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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