Intra-die process variation aware anomaly detection in FPGAs. Pino, Y., Jyothi, V., & French, M. In 2014 International Test Conference, pages 1-6, Oct, 2014. doi bibtex @INPROCEEDINGS{7035343,
author={Y. {Pino} and V. {Jyothi} and M. {French}},
booktitle={2014 International Test Conference},
title={Intra-die process variation aware anomaly detection in FPGAs},
year={2014},
volume={},
number={},
pages={1-6},
keywords={field programmable gate arrays;hardware-software codesign;integrated circuit testing;invasive software;logic design;VLSI;intradie process variation aware;nondestructive method;hardware trojans;VLSI layer;configurable logic blocks;switch blocks;chip under test;anomaly detection;Xili1nx Virtex-4;Virtex-5;Virtex-6 FPGA devices;Field programmable gate arrays;Trojan horses;Frequency measurement;Hardware;Delays;Correlation;Fabrics},
doi={10.1109/TEST.2014.7035343},
ISSN={1089-3539},
month={Oct},}
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