Timepix3: a 65K channel hybrid pixel readout chip with simultaneous ToA/ToT and sparse readout. Poikela, T, Plosila, J, Westerlund, T, Campbell, M, Gaspari, M D., Llopart, X, Gromov, V, Kluit, R, Beuzekom, M v., Zappon, F, Zivkovic, V, Brezina, C, Desch, K, Fu, Y, & Kruth, A Journal of Instrumentation, 9(05):C05013–C05013, May, 2014. ![Timepix3: a 65K channel hybrid pixel readout chip with simultaneous ToA/ToT and sparse readout [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi abstract bibtex The Timepix3, hybrid pixel detector (HPD) readout chip, a successor to the Timepix [1] chip, can record time-of-arrival (ToA) and time-over-threshold (ToT) simultaneously in each pixel. ToA information is recorded in a 14-bit register at 40 MHz and can be refined by a further 4 bits with a nominal resolution of 1.5625 ns (640 MHz). ToT is recorded in a 10-bit over-flow controlled counter at 40 MHz. Pixels can be programmed to record 14 bits of integral ToT and 10 bits of event counting, both at 40 MHz. The chip is designed in 130 nm CMOS and contains 256 × 256 pixel channels (55 × 55 µm 2). The chip, which has more than 170 M transistors, has been conceived as a general-purpose readout chip for HPDs used in a wide range of applications. Com-mon requirements of these applications are operation without a trigger signal, and sparse readout where only pixels containing event information are read out. A new architecture has been designed for sparse readout and can achieve a throughput of up to 40 Mhits/s/cm 2 . The flexible architecture offers readout schemes ranging from serial (one link) readout (40 Mbps) to faster parallel (up to 8 links) readout of 5.12 Gbps. In the ToA/ToT operation mode, readout is simultaneous with data acquisition thus keeping pixels sensitive at all times. The pixel matrix is formed by super pixel (SP) structures of 2 × 4 pixels. This optimizes resources by sharing the pixel readout logic which transports data from SPs to End-of-Column (EoC) using a 2-phase handshake protocol. To reduce power consumption in applications with a low duty cycle, an on-chip power pulsing scheme has been implemented. The logic switches bias currents of the analog front-ends in a se-quential manner, and all front-ends can be switched in 800 ns. The digital design uses a mixture of commercial and custom standard cell libraries and was verified using Open Verification Methodol-ogy (OVM) and commercial timing analysis tools. The analog front-end and a voltage-controlled oscillator for 1.5625 ns timing resolution have been designed using full custom techniques.
@article{Poikela2014,
title = {Timepix3: a {65K} channel hybrid pixel readout chip with simultaneous {ToA}/{ToT} and sparse readout},
volume = {9},
issn = {1748-0221},
url = {http://iopscience.iop.org/article/10.1088/1748-0221/9/05/C05013/meta},
doi = {10.1088/1748-0221/9/05/C05013},
abstract = {The Timepix3, hybrid pixel detector (HPD) readout chip, a successor to the Timepix [1] chip, can record time-of-arrival (ToA) and time-over-threshold (ToT) simultaneously in each pixel. ToA information is recorded in a 14-bit register at 40 MHz and can be refined by a further 4 bits with a nominal resolution of 1.5625 ns (640 MHz). ToT is recorded in a 10-bit over-flow controlled counter at 40 MHz. Pixels can be programmed to record 14 bits of integral ToT and 10 bits of event counting, both at 40 MHz. The chip is designed in 130 nm CMOS and contains 256 × 256 pixel channels (55 × 55 µm 2). The chip, which has more than 170 M transistors, has been conceived as a general-purpose readout chip for HPDs used in a wide range of applications. Com-mon requirements of these applications are operation without a trigger signal, and sparse readout where only pixels containing event information are read out. A new architecture has been designed for sparse readout and can achieve a throughput of up to 40 Mhits/s/cm 2 . The flexible architecture offers readout schemes ranging from serial (one link) readout (40 Mbps) to faster parallel (up to 8 links) readout of 5.12 Gbps. In the ToA/ToT operation mode, readout is simultaneous with data acquisition thus keeping pixels sensitive at all times. The pixel matrix is formed by super pixel (SP) structures of 2 × 4 pixels. This optimizes resources by sharing the pixel readout logic which transports data from SPs to End-of-Column (EoC) using a 2-phase handshake protocol. To reduce power consumption in applications with a low duty cycle, an on-chip power pulsing scheme has been implemented. The logic switches bias currents of the analog front-ends in a se-quential manner, and all front-ends can be switched in 800 ns. The digital design uses a mixture of commercial and custom standard cell libraries and was verified using Open Verification Methodol-ogy (OVM) and commercial timing analysis tools. The analog front-end and a voltage-controlled oscillator for 1.5625 ns timing resolution have been designed using full custom techniques.},
number = {05},
urldate = {2017-12-17},
journal = {Journal of Instrumentation},
author = {Poikela, T and Plosila, J and Westerlund, T and Campbell, M and Gaspari, M De and Llopart, X and Gromov, V and Kluit, R and Beuzekom, M van and Zappon, F and Zivkovic, V and Brezina, C and Desch, K and Fu, Y and Kruth, A},
month = may,
year = {2014},
keywords = {CMOS readout of gaseous detectors, Front-end electronics for detec-tor readout, VLSI circuits},
pages = {C05013--C05013},
}
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