@inproceedings{poss12rapido,
	Abstract = {The EU Apple-CORE project has explored the design and implementation of novel general-purpose many-core chips featuring hardware microthreading and hardware support for concurrency management. The introduction of the latter in the cores ISA has required simultaneous investigation into compilers and multiple layers of the software stack, including operating systems. The main challenge in such vertical approaches is the cost of implementing simultaneously a detailed simulation of new hardware components and a complete system platform suitable to run large software benchmaks. In this paper, we describe our use case and our solutions to this challenge.},
	Acmid = {2162134},
	Author = {Poss, Raphael and Lankamp, Mike and Uddin, M. Irfan and S\'{y}kora, Jaroslav and Kafka, Leo\v{s}},
	Booktitle = {Proc. 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools},


	Doi = {10.1145/2162131.2162134}, Urldoi = {http://dx.doi.org/10.1145/2162131.2162134},
	Isbn = {978-1-4503-1114-4},
	Keywords = {hardware multithreading, hardware/software co-design, many-core architecture, simulation, system design, system evaluation, system-on-chip design, vertical approach},
	Location = {Paris, France},
	Month = {January},
	Numpages = {8},
	Pages = {17--24},
	Publisher = {ACM},
	Read = {1},
	Series = {RAPIDO '12},
	Title = {Heterogeneous integration to simplify many-core architecture simulations},
	Urllocal = {pub/poss.12.rapido.pdf},
	Year = {2012},
	
	
	}

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