@inproceedings{poss13samos,
	Abstract = {This article presents MGSim, an open source discrete event simulator for on-chip hardware components developed at the University of Amsterdam. MGSim is used as research and teaching vehicle to study the fine-grained hardware/software interactions on many-core chips with and without hardware multithreading. MGSim's component library includes support for core models with different instruction sets, a configurable multi-core interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a multi-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks.},
	Author = {Raphael Poss and Mike Lankamp and Qiang Yang and Jian Fu and Irfan Uddin and Chris Jesshope},
	Booktitle = {Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS XIII)},


	Doi = {10.1109/SAMOS.2013.6621109}, Urldoi = {http://dx.doi.org/10.1109/SAMOS.2013.6621109},
	Month = {July},
	Pages = {80--87},
	Publisher = {IEEE},
	Read = {1},
	Title = {{MGSim}---A simulation Environment for Multi-Core Research and Education},
	Urllocal = {pub/poss.13.samos.pdf},
	Year = {2013},
	}

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