Customization of Application Speci c Heterogeneous MultiPipeline Processors. Radhakrishnan, S.; Guo, H.; and Parameswaran, S. In Design, Automation and Test in Europe Conference and Exhibition (DATE '06), pages 6 pages, Munich, Germany, 2006. IEEE Comput. Soc.
abstract   bibtex   
In this paper we propose application specific instruction set processors with heterogeneous multiple pipelines to efficiently exploit the available parallelism at instruction level. We have developed a design system based on the Thumb processor architecture. Given an application specified in C language, the design system can generate a processor with a number of pipelines specifically suitable to the application, and the parallel code associated with the processor. Each pipeline in such a processor is customized, and implements its own special instruction set so that the instructions can be executed in parallel with low hardware overhead. Our simulations and experiments with a group of benchmarks, largely from Mibench suite, show that on average, 77% performance improvement can be achieved compared to a single pipeline ASIP, with the overheads of 49% on area, 51% on leakage power, 17% on switching activity, and 69% on code size (20 refs.)
@inproceedings{ SwarnaDate06,
  author = {Radhakrishnan, Swarana and Guo, Hui and Parameswaran, Sri},
  title = {Customization of Application Speci c Heterogeneous MultiPipeline
	Processors.},
  booktitle = { Design, Automation and Test in Europe Conference and Exhibition
	(DATE '06)},
  year = {2006},
  pages = {6 pages},
  address = {Munich, Germany},
  publisher = {IEEE Comput. Soc},
  abstract = {In this paper we propose application specific instruction set processors
	with heterogeneous multiple pipelines to efficiently exploit the
	available parallelism at instruction level. We have developed a design
	system based on the Thumb processor architecture. Given an application
	specified in C language, the design system can generate a processor
	with a number of pipelines specifically suitable to the application,
	and the parallel code associated with the processor. Each pipeline
	in such a processor is customized, and implements its own special
	instruction set so that the instructions can be executed in parallel
	with low hardware overhead. Our simulations and experiments with
	a group of benchmarks, largely from Mibench suite, show that on average,
	77% performance improvement can be achieved compared to a single
	pipeline ASIP, with the overheads of 49% on area, 51% on leakage
	power, 17% on switching activity, and 69% on code size (20 refs.)},
  pdf = {http://www.cse.unsw.edu.au/~sridevan/index_files/07A_4.pdf}
}
Downloads: 0