Application Specific Forwarding Network and Instruction Encoding for Multi-pipe ASIPs. Radhakrishnan, S.; Guo, H.; Parameswaran, S.; and Ignjatovic, A. In International Conference on Hardware/Software Codesign and Systems Synthesis (CODES + ISSS '06), pages 6, Seoul, Korea, 2006.
abstract   bibtex   
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instruction encoding schemes for multi-pipe Application Specific Instruction-Set Processors (ASIPs). Forwarding is a popular technique to reduce data hazards in the pipeline to improve performance and is applied in almost all modern processor designs; but it is very area expensive. Instruction encoding schemes have a direct impact on code size; an efficient encoding method can lead to a small instruction width, and hence reducing the code size. We propose application specific techniques to reduce forwarding networks and instruction widths for ASIPs with multiple pipelines. By these design techniques, it is possible to reduce area, code size, and even power consumption (due to reduced area), without costing any performance. Our experiments, on a set of benchmarks using the proposed customization approaches show that, on average, there are 27% savings on area, 30% on leakage power, 16.7% on code size, and at the same time, performance even improves by 4% because of the reduced clock period.
@inproceedings{ Swarna06,
  author = {Radhakrishnan, Swarnalatha and Guo, Hui and Parameswaran, Sri and
	Ignjatovic, Aleksandar},
  title = {Application Specific Forwarding Network and Instruction Encoding
	for Multi-pipe ASIPs},
  booktitle = {International Conference on Hardware/Software Codesign and Systems
	Synthesis (CODES + ISSS '06)},
  year = {2006},
  pages = {6},
  address = {Seoul, Korea},
  abstract = {Small area and code size are two critical design issues in most of
	embedded system designs. In this paper, we tackle these issues by
	customizing forwarding networks and instruction encoding schemes
	for multi-pipe Application Specific Instruction-Set Processors (ASIPs).
	Forwarding is a popular technique to reduce data hazards in the pipeline
	to improve performance and is applied in almost all modern processor
	designs; but it is very area expensive. Instruction encoding schemes
	have a direct impact on code size; an efficient encoding method can
	lead to a small instruction width, and hence reducing the code size.
	We propose application specific techniques to reduce forwarding networks
	and instruction widths for ASIPs with multiple pipelines. By these
	design techniques, it is possible to reduce area, code size, and
	even power consumption (due to reduced area), without costing any
	performance. Our experiments, on a set of benchmarks using the proposed
	customization approaches show that, on average, there are 27% savings
	on area, 30% on leakage power, 16.7% on code size, and at the same
	time, performance even improves by 4% because of the reduced clock
	period.}
}
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