{"_id":"s7aseqTkkEn9riu44","bibbaseid":"rajagopala-sass-schmidt-designconsiderationsformappingfpgahighlevelsynthesisalgorithmstonextgenerationmemorydevices-2019","author_short":["Rajagopala, A. D.","Sass, R.","Schmidt, A. G."],"bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"firstnames":["Abhi","D."],"propositions":[],"lastnames":["Rajagopala"],"suffixes":[]},{"firstnames":["Ron"],"propositions":[],"lastnames":["Sass"],"suffixes":[]},{"firstnames":["Andrew","G."],"propositions":[],"lastnames":["Schmidt"],"suffixes":[]}],"booktitle":"International Symposium on Memory Systems (MEMSYS)","title":"Design Considerations for Mapping FPGA High-Level Synthesis Algorithms to Next-Generation Memory Devices","year":"2019","bibtex":"@inproceedings{rajagopala2019b,\n\tauthor = {Abhi D. Rajagopala and Ron Sass and Andrew G. Schmidt},\n\tbooktitle = {International Symposium on Memory Systems (MEMSYS)},\n\ttitle = {Design Considerations for Mapping FPGA High-Level Synthesis Algorithms to Next-Generation Memory Devices},\n\tyear = {2019}}\n\n","author_short":["Rajagopala, A. D.","Sass, R.","Schmidt, A. G."],"key":"rajagopala2019b","id":"rajagopala2019b","bibbaseid":"rajagopala-sass-schmidt-designconsiderationsformappingfpgahighlevelsynthesisalgorithmstonextgenerationmemorydevices-2019","role":"author","urls":{},"metadata":{"authorlinks":{}}},"bibtype":"inproceedings","biburl":"https://bibbase.org/network/files/yPTXAsnfTw5JximEx","dataSources":["vzpCDFTCjn9o9Hnqu","oiMbyDLiSCRNWoDbD","9TFdJzWYEyHmnd4HD"],"keywords":[],"search_terms":["design","considerations","mapping","fpga","high","level","synthesis","algorithms","next","generation","memory","devices","rajagopala","sass","schmidt"],"title":"Design Considerations for Mapping FPGA High-Level Synthesis Algorithms to Next-Generation Memory Devices","year":2019}