Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. Ramanarayanan, R., Degalahal, V., Ramakrishnan, K., Kim, J., Narayanan, V., Xie, Y., Irwin, M. J., & Unlu, K. IEEE Trans. Dependable Sec. Comput., 6(3):202-216, 2009.
Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. [link]Link  Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. [link]Paper  bibtex   
@article{journals/tdsc/RamanarayananDRKNXIU09,
  added-at = {2016-03-03T00:00:00.000+0100},
  author = {Ramanarayanan, Rajaraman and Degalahal, Vijay and Ramakrishnan, Krishnan and Kim, Jungsub and Narayanan, Vijaykrishnan and Xie, Yuan and Irwin, Mary Jane and Unlu, Kenan},
  biburl = {http://www.bibsonomy.org/bibtex/29ce141a9a45f1032ca04c59419379a73/dblp},
  ee = {http://doi.ieeecomputersociety.org/10.1109/TDSC.2007.70231},
  interhash = {bbb10d7f33d913bce179c71507f1a388},
  intrahash = {9ce141a9a45f1032ca04c59419379a73},
  journal = {IEEE Trans. Dependable Sec. Comput.},
  keywords = {dblp},
  number = 3,
  pages = {202-216},
  timestamp = {2016-03-04T11:42:11.000+0100},
  title = {Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.},
  url = {http://dblp.uni-trier.de/db/journals/tdsc/tdsc6.html#RamanarayananDRKNXIU09},
  volume = 6,
  year = 2009
}

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