18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS. Ramanarayanan, R., Mathew, S., Sheikh, F., Srinivasan, S., Agarwal, A., Hsu, S., Kaul, H., Anders, M., Erraguntla, V., & Krishnamurthy, R. In 2010 Proceedings of ESSCIRC, pages 210–213, September, 2010.
doi  abstract   bibtex   
A multi-mode Secure Hashing Algorithm (SHA) accelerator is fabricated in 45nm CMOS and occupies 0.0625mm2 with 18Gbps throughput and total power consumption of 50mW. The reconfigurable hardware accelerator computes SHA-1/224/256/384/512 message-digest using unified SHA bit-slices and configurable compression circuits resulting in 40% area reduction and \textless;3% performance overhead for reconfiguration with 23Gbps peak throughput in SHA-224/256 modes. SHA frequency ranges from 21MHz-1.8GHz across 320mV-1.35V supply voltage range.
@inproceedings{ramanarayanan_18gbps_2010,
	title = {18Gbps, 50mW reconfigurable multi-mode {SHA} {Hashing} accelerator in 45nm {CMOS}},
	doi = {10.1109/ESSCIRC.2010.5619892},
	abstract = {A multi-mode Secure Hashing Algorithm (SHA) accelerator is fabricated in 45nm CMOS and occupies 0.0625mm2 with 18Gbps throughput and total power consumption of 50mW. The reconfigurable hardware accelerator computes SHA-1/224/256/384/512 message-digest using unified SHA bit-slices and configurable compression circuits resulting in 40\% area reduction and {\textless};3\% performance overhead for reconfiguration with 23Gbps peak throughput in SHA-224/256 modes. SHA frequency ranges from 21MHz-1.8GHz across 320mV-1.35V supply voltage range.},
	booktitle = {2010 {Proceedings} of {ESSCIRC}},
	author = {Ramanarayanan, R. and Mathew, S. and Sheikh, F. and Srinivasan, S. and Agarwal, A. and Hsu, S. and Kaul, H. and Anders, M. and Erraguntla, V. and Krishnamurthy, R.},
	month = sep,
	year = {2010},
	pages = {210--213}
}

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