Efficient RTL Power Estimation for Large Designs

Efficient RTL Power Estimation for Large Designs. Ravi, S., Raghunathan, A., & Chakradhar, S. T. In 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pages 431–439, 2003.

Paper doi bibtex

@inproceedings{DBLP:conf/vlsid/RaviRC03a,
  author    = {Srivaths Ravi and
               Anand Raghunathan and
               Srimat T. Chakradhar},
  title     = {Efficient {RTL} Power Estimation for Large Designs},
  booktitle = {16th International Conference on {VLSI} Design {(VLSI} Design 2003),
               4-8 January 2003, New Delhi, India},
  pages     = {431--439},
  year      = {2003},
  crossref  = {DBLP:conf/vlsid/2003},
  url       = {https://doi.org/10.1109/ICVD.2003.1183173},
  doi       = {10.1109/ICVD.2003.1183173},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/RaviRC03a},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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