SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing. Ren, A., Li, J., Li, Z., Ding, C., Qian, X., Qiu, Q., Yuan, B., & Wang, Y. arXiv:1611.05939 [cs], November, 2016. arXiv: 1611.05939
SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing [link]Paper  abstract   bibtex   
With the recent advance of wearable devices and Internet of Things (IoTs), it becomes attractive to implement the Deep Convolutional Neural Networks (DCNNs) in embedded and portable systems. Currently, executing the software-based DCNNs requires high-performance servers, restricting the widespread deployment on embedded and mobile IoT devices. To overcome this obstacle, considerable research efforts have been made to develop highly-parallel and specialized DCNN accelerators using GPGPUs, FPGAs or ASICs. Stochastic Computing (SC), which uses a bit-stream to represent a number within [-1, 1] by counting the number of ones in the bit-stream, has high potential for implementing DCNNs with high scalability and ultra-low hardware footprint. Since multiplications and additions can be calculated using AND gates and multiplexers in SC, significant reductions in power (energy) and hardware footprint can be achieved compared to the conventional binary arithmetic implementations. The tremendous savings in power (energy) and hardware resources allow immense design space for enhancing scalability and robustness for hardware DCNNs.
@article{ren_sc-dcnn:_2016,
	title = {{SC}-{DCNN}: {Highly}-{Scalable} {Deep} {Convolutional} {Neural} {Network} using {Stochastic} {Computing}},
	shorttitle = {{SC}-{DCNN}},
	url = {http://arxiv.org/abs/1611.05939},
	abstract = {With the recent advance of wearable devices and Internet of Things (IoTs), it becomes attractive to implement the Deep Convolutional Neural Networks (DCNNs) in embedded and portable systems. Currently, executing the software-based DCNNs requires high-performance servers, restricting the widespread deployment on embedded and mobile IoT devices. To overcome this obstacle, considerable research efforts have been made to develop highly-parallel and specialized DCNN accelerators using GPGPUs, FPGAs or ASICs. Stochastic Computing (SC), which uses a bit-stream to represent a number within [-1, 1] by counting the number of ones in the bit-stream, has high potential for implementing DCNNs with high scalability and ultra-low hardware footprint. Since multiplications and additions can be calculated using AND gates and multiplexers in SC, significant reductions in power (energy) and hardware footprint can be achieved compared to the conventional binary arithmetic implementations. The tremendous savings in power (energy) and hardware resources allow immense design space for enhancing scalability and robustness for hardware DCNNs.},
	language = {en},
	urldate = {2019-03-23TZ},
	journal = {arXiv:1611.05939 [cs]},
	author = {Ren, Ao and Li, Ji and Li, Zhe and Ding, Caiwen and Qian, Xuehai and Qiu, Qinru and Yuan, Bo and Wang, Yanzhi},
	month = nov,
	year = {2016},
	note = {arXiv: 1611.05939},
	keywords = {⛔ No DOI found}
}

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